Inventor · disambiguated record
Chew Hoe Ang
Also filed as: ANG CHEW H · ANG CHEW-HOE
29 granted patents·7 pending applications·794 citations·filing 2001–2008
97Inventor score
Top patents by PatentIndex Score
36 records- 0198US6743291B2Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 1, 2004·125 cites·28 claims
- 0296US7479425B2Method for forming high-K charge storage deviceCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jan 20, 2009·40 cites·28 claims
- 0393US6664156B1Method for forming L-shaped spacers with precise width controlCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·76 cites·17 claims
- 0493US6632712B1Method of fabricating variable length vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 14, 2003·89 cites·31 claims
- 0590US7202140B1Method to fabricate Ge and Si devices together for performance enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Apr 10, 2007·21 cites·20 claims
- 0690US6468851B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 22, 2002·55 cites·39 claims
- 0788US6670248B1Triple gate oxide process with high-k gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 30, 2003·48 cites·15 claims
- 0887US6734082B2Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shapeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted May 11, 2004·45 cites·28 claims
- 0987US6709912B1Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimizationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·53 cites·27 claims
- 1084US6762085B2Method of forming a high performance and low cost CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 13, 2004·36 cites·27 claims
- 1183US6830971B2High K artificial lattices for capacitor applications to use in CU or AL BEOLCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 14, 2004·26 cites·40 claims
- 1281US7562318B2Test structure for automatic dynamic negative-bias temperature instability testingCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Jul 14, 2009·6 cites·22 claims
- 1378US6403425B1Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·25 cites·36 claims
- 1477US7103861B2Test structure for automatic dynamic negative-bias temperature instability testingCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Sep 5, 2006·16 cites·8 claims
- 1573US7176094B2Ultra-thin gate oxide through post decoupled plasma nitridation annealCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 13, 2007·15 cites·15 claims
- 1673US6664153B2Method to fabricate a single gate with dual work-functionsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·18 cites·22 claims
- 1773US6429109B1Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gateCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 6, 2002·18 cites·35 claims
- 1872US6841441B2Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jan 11, 2005·12 cites·37 claims
- 1971US6610575B1Forming dual gate oxide thickness on vertical transistors by ion implantationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·16 cites·47 claims
- 2068US6605501B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 12, 2003·14 cites·36 claims
- 2163US7795046B2Method and apparatus for monitoring endcap pullbackADVANCED MICRO DEVICES INC·Filed 2007·Granted Sep 14, 2010·1 cites·23 claims
- 2262US6610604B1Method of forming small transistor gates by using self-aligned reverse spacer as a hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·10 cites·30 claims
- 2356US6586314B1Method of forming shallow trench isolation regions with improved corner roundingCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 1, 2003·7 cites·29 claims
- 2455US7095073B2High K artificial lattices for capacitor applications to use in Cu or Al BEOLCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Aug 22, 2006·4 cites·8 claims
- 2554US6544848B1Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacersCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 8, 2003·6 cites·25 claims
- 2650US2009023280A1Method for forming high-k charge storage deviceCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2748US7132878B2Charge pump current sourceCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Nov 7, 2006·7 cites·40 claims
- 2848US2008087958A1Semiconductor device with doped transistorCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 2947US7022625B2Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetrationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 4, 2006·4 cites·13 claims
- 3047US6828082B2Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 7, 2004·1 cites·51 claims
- 3146US7326609B2Semiconductor device and fabrication methodCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Feb 5, 2008·0 cites·10 claims
- 3243US2005089777A1Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 3343US2005101083A1Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 3438US2004266155A1Formation of small gates beyond lithographic limitsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 3538US2004029321A1Method for forming gate insulating layer having multiple dielectric constants and multiple equivalent oxide thicknessesCHARTERED SEMICONDUCTOR MFG·Filed 2002·Application pending·0 cites
- 3635US2007090484A1Integrated circuit stress control systemCHARTERED SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →