Semiconductor device with doped transistor

Abstract

A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

1 . A semiconductor device, comprising: 
 a substrate;    a first region in the substrate;    a double diffused source/drain in the first region;    a first region gate dielectric in the first region;    a first region gate on the first region gate dielectric;    a second region in the substrate;    a second region gate in the second region, the second region gate being thinner than the first region gate; and    a second region source/drain in the second region.    
     
     
         2 . The semiconductor device of  claim 1  wherein the double diffused source/drain is self-aligned.  
     
     
         3 . The semiconductor device of  claim 1  further comprising a second region gate dielectric in the second region.  
     
     
         4 . The semiconductor device of  claim 1  further comprising a shallow source/drain in the second region.  
     
     
         5 . The semiconductor device of  claim 1  wherein the first region gate uses doped polysilicon or metal.  
     
     
         6 . A semiconductor device, comprising: 
 a substrate;    a high voltage device region in the substrate;    a double diffused source/drain in the high voltage device region;    a high voltage gate dielectric in the high voltage device region having a thickness greater than 400 Å;    a high voltage gate on the high voltage gate dielectric a high voltage source/drain;    a low voltage device region in the substrate;    a low voltage gate in the low voltage device region;    a low voltage spacer around the low voltage gate;    a low voltage source/drain in the low voltage device region; and    shallow trench isolations between and around the high voltage device region and the low voltage device region.    
     
     
         7 . The semiconductor device of  claim 6  wherein the double diffused source/drain is self-aligned.  
     
     
         8 . The semiconductor device of  claim 6  further comprising a low voltage gate dielectric in the low voltage device region.  
     
     
         9 . The semiconductor device of  claim 6  further comprising a low voltage lightly doped source/drain in the low voltage device region.  
     
     
         10 . The semiconductor device of  claim 6  wherein the high voltage gate uses doped polysilicon or metal.