Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing

Abstract

A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

1 . A method of fabricating first and second gates, comprising the steps of: 
 providing a substrate having a gate dielectric layer formed thereover; the substrate having a first gate region and a second gate region;    forming a thin first gate layer over the gate dielectric layer;    masking the thin first gate layer within the second gate region to expose a portion of the thin first gate layer within the first gate region;    converting the exposed portion of the thin first gate layer to a thin third gate layer portion;    forming a second gate layer over the thin first and third gate layer portions;    patterning the second gate layer and the first and third gate layer portions to form a first gate within first gate region and a second gate within second gate region.    
   
   
       2 - 37 . (canceled)  
   
   
       38 . A dual gate structure, comprising: 
 a substrate having a gate dielectric layer formed thereover; the substrate having a first gate region and a second gate region each over a non-implanted portion of the substrate;    a first gate over the gate dielectric layer within the first gate region; the first gate comprising a lower implanted first-gate layer portion and an upper first-gate layer portion; and    a second gate over the gate dielectric layer within the second gate region; the second gate comprising a lower non-implanted second-gate layer portion and an upper second-gate layer portion.    
   
   
       39 . The structure of  claim 38 , wherein the substrate is comprised of silicon or germanium; the gate dielectric layer is comprised of grown oxide or a dielectric material having a dielectric constant of greater than about 3.0; the lower implanted first-gate layer portion is comprised of metal silicide or germanium silicide; the lower non-implanted second-gate layer portion is comprised of poly or amorphous silicon; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal.  
   
   
       40 . The structure of  claim 38 , wherein the substrate is comprised of silicon; the gate dielectric layer is comprised of grown oxide; the lower implanted first-gate layer portion is comprised of metal silicide or germanium silicide; the lower non-implanted second-gate layer portion is comprised of poly or alpha-silicon; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or alpha-silicon.  
   
   
       41 . The structure of  claim 38 , wherein the gate dielectric layer is from about 10 to 100 Å thick; the lower implanted first-gate layer portion and lower non-implanted second-gate layer portion are each from about 100 to 800 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each from about 1000 to 1500 Å thick.  
   
   
       42 . The structure of  claim 38 , wherein the gate dielectric layer is from about 10 to 20 Å thick; the lower implanted first-gate layer portion and lower non-implanted second-gate layer portion are each from about 200 to 500 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each from about 1000 to 1500 Å thick.  
   
   
       43 . The structure of  claim 38 , including an isolation structure within the substrate, dividing the first and second gate regions.  
   
   
       44 . The structure of  claim 38 , including a shallow trench isolation structure (STI) within the substrate, dividing the first and second gate regions.  
   
   
       45 . The structure of  claim 38 , wherein the first gate is a poly/metal silicide stack; a poly/germanium silicide stack; a metal/metal silicide stack; or a metal/germanium silicide stack.  
   
   
       46 . The structure of  claim 38 , wherein the lower implanted first-gate layer portion is comprised of germanium silicate, tungsten silicate, tantalum silicate or molybdenum silicate; the lower non-implanted second-gate layer portion is comprised of germanium, tungsten, tantalum or molybdenum; the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly, tungsten, tantalum, molybdenum or tungsten silicate.  
   
   
       47 . The structure of  claim 38 , wherein the substrate is comprised of silicon; the gate dielectric layer is comprised of grown oxide; the lower implanted first-gate layer portion is comprised of tungsten silicate; the lower non-implanted second-gate layer portion is comprised of tungsten; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of a metal.  
   
   
       48 . The structure of  claim 38 , wherein the upper first-gate layer portion and upper second-gate layer portion are each comprised of a metal silicide or germanium silicide.  
   
   
       49 . A dual gate structure, comprising: 
 a silicon or germanium substrate having a gate dielectric layer formed thereover; the substrate having a first gate region and a second gate region each over a non-implanted portion of the substrate; the gate dielectric layer being comprised of grown oxide or a dielectric material having a dielectric constant of greater than about 3.0;    a first gate over the gate dielectric layer within the first gate region; the first gate comprising a lower implanted first-gate layer portion and an upper first-gate layer portion; and    a second gate over the gate dielectric layer within the second gate region; the second gate comprising a lower non-implanted second-gate layer portion and an upper second-gate layer portion.    
   
   
       50 . The structure of  claim 49 , wherein; the gate dielectric layer is comprised of grown oxide; the lower implanted first-gate layer portion is comprised of metal silicide or germanium silicide; the lower non-implanted second-gate layer portion is comprised of poly or amorphous silicon; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal.  
   
   
       51 . The structure of  claim 49 , wherein the substrate is comprised of silicon; the gate dielectric layer is comprised of grown oxide; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly.  
   
   
       52 . The structure of  claim 49 , wherein the gate dielectric layer is from about 10 to 100 Å thick; the lower implanted first-gate layer portion and the lower non-implanted second-gate layer portion are each from about 100 to 800 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal are each from about 1000 to 2000 Å thick.  
   
   
       53 . The structure of  claim 49 , wherein the gate dielectric layer is from about 10 to 20 Å thick; the lower implanted first-gate layer portion and the lower non-implanted second-gate layer portion are each from about 200 to 500 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal are each from about 1000 to 1500 Å thick.  
   
   
       54 . The structure of  claim 49 , including an isolation structure within the substrate, dividing the first and second gate regions.  
   
   
       55 . The structure of  claim 49 , including a shallow trench isolation structure (STI) within the substrate, dividing the first and second gate regions.  
   
   
       56 . The structure of  claim 49 , wherein the lower implanted first-gate layer portion is formed of metal silicide or germanium silicide.  
   
   
       57 . The structure of  claim 49 , wherein the first gate is a poly/metal silicide stack; a poly/germanium silicide stack; a metal/metal silicide stack; or a metal/germanium silicide stack.  
   
   
       58 . The structure of  claim 49 , wherein the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly, tungsten, tantalum, molybdenum or tungsten silicate.