Inventor · disambiguated record
Jin Ping Liu
Also filed as: LIU JIN · LIU JIN PING
56 granted patents·14 pending applications·819 citations·filing 1999–2019
98Inventor score
Files withGLOBALFOUNDRIES INC39CHARTERED SEMICONDUCTOR MFG8IBM4EDISON OPTO DONGGUAN CO LTD3LENOVO BEIJING CO LTD3
Top patents by PatentIndex Score
70 records- 0198US9406676B2Method for forming single diffusion breaks between finFET devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 2, 2016·41 cites·14 claims
- 0298US9362180B2Integrated circuit having multiple threshold voltagesGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 7, 2016·425 cites·20 claims
- 0397US9620380B1Methods for fabricating integrated circuits using self-aligned quadruple patterningGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 11, 2017·31 cites·18 claims
- 0497US9466723B1Liner and cap layer for placeholder source/drain contact structure planarization and replacementGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 11, 2016·31 cites·15 claims
- 0597US9343371B1Fabricating fin structures with doped middle portionsGLOBALFOUNDRIES INC·Filed 2015·Granted May 17, 2016·17 cites·20 claims
- 0697US8927989B2Voltage contrast inspection of deep trench isolationIBM·Filed 2012·Granted Jan 6, 2015·86 cites·8 claims
- 0795US9443956B2Method for forming air gap structure using carbon-containing spacerGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 13, 2016·22 cites·21 claims
- 0894US9087870B2Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 21, 2015·18 cites·19 claims
- 0992US9455201B2Integration method for fabrication of metal gate based multiple threshold voltage devices and circuitsGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 27, 2016·18 cites·17 claims
- 1092US7947546B2Implant damage control by in-situ C doping during SiGe epitaxy for device applicationsCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted May 24, 2011·17 cites·52 claims
- 1191US9236481B1Semiconductor device and methods of forming fins and gates with ultraviolet curingGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 12, 2016·6 cites·20 claims
- 1290US9196710B2Integrated circuits with relaxed silicon / germanium finsGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 24, 2015·11 cites·19 claims
- 1387US9373535B2T-shaped fin isolation region and methods of fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 21, 2016·7 cites·19 claims
- 1484US9129987B2Replacement low-K spacerGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 8, 2015·7 cites·15 claims
- 1581US9040380B2Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2013·Granted May 26, 2015·6 cites·20 claims
- 1680US9401416B2Method for reducing gate height variation due to overlapping masksGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 26, 2016·4 cites·21 claims
- 1778US9263520B2Facilitating fabricating gate-all-around nanowire field-effect transistorsGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 16, 2016·3 cites·16 claims
- 1874US9647073B2Transistor structures and fabrication methods thereofGLOBALFOUNDRIES INC·Filed 2014·Granted May 9, 2017·2 cites·14 claims
- 1973US9312145B2Conformal nitridation of one or more fin-type transistor layersGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 12, 2016·2 cites·18 claims
- 2073US9142640B1Containment structure for epitaxial growth in non-planar semiconductor structureGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 22, 2015·3 cites·10 claims
- 2173US7776699B2Strained channel transistor structure and methodCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Aug 17, 2010·3 cites·28 claims
- 2272US9230822B1Uniform gate height for mixed-type non-planar semiconductor devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 5, 2016·2 cites·9 claims
- 2371US9076645B1Method of fabricating an interlayer structure of increased elasticity modulusGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 7, 2015·2 cites·20 claims
- 2469US9942957B1Light emitting diode driving circuitEDISON OPTO DONGGUAN CO LTD·Filed 2017·Granted Apr 10, 2018·2 cites·9 claims
- 2569US8652892B2Implant damage control by in-situ C doping during sige epitaxy for device applicationsLIU JIN PING·Filed 2011·Granted Feb 18, 2014·2 cites·23 claims
- 2669US6995078B2Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatchCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Feb 7, 2006·12 cites·24 claims
- 2768US9698269B2Conformal nitridation of one or more fin-type transistor layersGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 4, 2017·1 cites·13 claims
- 2868US9490197B2Three dimensional organic or glass interposerIBM·Filed 2014·Granted Nov 8, 2016·2 cites·19 claims
- 2968US9147696B2Devices and methods of forming finFETs with self aligned fin formationGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 29, 2015·2 cites·7 claims
- 3066US9698483B2Aerial device and method for setting aerial deviceLENOVO BEIJING CO LTD·Filed 2014·Granted Jul 4, 2017·3 cites·10 claims
- 3163US9142673B2Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectricsGLOBAL FOUNDRIES INC·Filed 2013·Granted Sep 22, 2015·1 cites·6 claims
- 3262US9171848B2Deep trench MIM capacitor and moat isolation with epitaxial semiconductor wafer schemeIBM·Filed 2013·Granted Oct 27, 2015·1 cites·20 claims
- 3362US8486800B2Trench capacitor and method for producing the sameLIU JIN·Filed 2009·Granted Jul 16, 2013·2 cites·13 claims
- 3462US7863141B2Integration for buried epitaxial stressorCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Jan 4, 2011·2 cites·21 claims
- 3562US7346638B2Filtering, equalization, and power estimation for enabling higher speed signal transmissionUNIV TEXAS·Filed 2003·Granted Mar 18, 2008·8 cites·29 claims
- 3655US9293382B2Voltage contrast inspection of deep trench isolationGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 22, 2016·0 cites·5 claims
- 3754US9142422B2Methods of fabricating defect-free semiconductor structuresGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 22, 2015·0 cites·13 claims
- 3854US8343864B2DRAM with schottky barrier FET and MIM trench capacitorIBM·Filed 2011·Granted Jan 1, 2013·1 cites·20 claims
- 3953US11327845B2Image synchronization method and device, and serverGUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP LTD·Filed 2019·Granted May 10, 2022·0 cites·20 claims
- 4053US10204991B2Transistor structures and fabrication methods thereofGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 12, 2019·0 cites·11 claims
- 4152US7166522B2Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatchCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jan 23, 2007·3 cites·25 claims
- 4250US9368342B2Defect-free relaxed covering layer on semiconductor substrate with lattice mismatchGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 14, 2016·0 cites·10 claims
- 4349US2016225771A1Fabricating fin structures with doped middle portionsGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 4448US8754447B2Strained channel transistor structure and methodLIU JIN PING·Filed 2010·Granted Jun 17, 2014·0 cites·25 claims
- 4548US7064037B2Silicon-germanium virtual substrate and method of fabricating the sameCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jun 20, 2006·3 cites·27 claims
- 4648US2015357332A1Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectricsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 4747US9472465B2Methods of fabricating integrated circuitsGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 18, 2016·0 cites·14 claims
- 4847US8790980B2Implant damage control by in-situ C doping during sige epitaxy for device applicationsGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Jul 29, 2014·0 cites·20 claims
- 4947US2008159374A1Filtering, equalization, and powers estimation for enabling higher speed signal transmissionLIN XIAOFENG·Filed 2008·Application pending·0 cites
- 5047US2016099344A1Facilitating fabricating gate-all-around nanowire field-effect transistorsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
Showing the top 50 of 70 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →