Filtering, equalization, and powers estimation for enabling higher speed signal transmission

Abstract

An equalizer consistent with certain embodiments has a differential analog tapped delay line made of a plurality of N series connected analog delay cells. Each cell has a pair of differential inputs and a pair of differential outputs. The delay line receives an input signal to be equalized. The differential input pair of the nth cell is connected to the differential output pair of the (n−1)th cell such that current is mirrored from the output pair to the input pair to form N−1 differential taps. Each one of N−1 differential input multiplying digital to analog converters (MDAC) is connected at its differential input at each differential tap, with each MDAC multiplying an analog signal at its input by a digital weighting factor to produce an output at a differential output. A differential slicer receives a sum of the differential outputs from each of the MDACs and produces an equalized output. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

1 . An equalizer, comprising:
 a differential analog tapped delay line comprising a plurality of N series connected analog delay cells, wherein each cell includes a pair of differential inputs and a pair of differential outputs, and wherein the differential analog tapped delay line receives an input signal to be equalized;   wherein, the differential input pair of the nth cell is connected to the differential output pair of the (n−1)th cell such that current is mirrored from the output pair to the input pair to form N−1 differential taps;   N−1 differential input multiplying digital to analog converters (MDAC), one connected at its differential input at each differential tap, each MDAC multiplying an analog signal at its input by a digital weighting factor value to produce an output at a differential output; and   a differential slicer receiving a sum of the differential outputs from each of the MDACs and producing an equalized output.   
   
   
       2 . The equalizer according to  claim 1 , wherein the delay of each of the delay cells comprises at least one delay selected from the group consisting of a delay of less than one symbol time of a signal being equalized, a delay of approximately one eighth of one symbol time of a signal being equalized, and a tunable delay. 
   
   
       3 . The equalizer according to  claim 1 , wherein the equalizer has a finite impulse response. 
   
   
       4 . The equalizer according to  claim 1 , wherein the quality factor (Q) of each of the delay elements is tunable. 
   
   
       5 . The equalizer according to  claim 1 , further comprising a differential transconductor circuit coupled to the input of the first delay cell of the delay line. 
   
   
       6 . The equalizer according to  claim 1 , further comprising a current mirror circuit serving as a termination to the output of the delay line. 
   
   
       7 . The equalizer according to  claim 1 , wherein the digital weighting factor values are represented as thermometer coded digital values. 
   
   
       8 . The equalizer according to  claim 1 , wherein at least one of the digital weighting factors is a negative value, and wherein the negative value is represented by one of represented by either a bit value of the digital weighting factor, or by a reversed connection between an the MDAC and the digital tap. 
   
   
       9 . The equalizer according to  claim 1 , further comprising:
 a power spectrum estimator receiving the input signal to be equalized, estimating the power spectrum thereof, and producing an error signal output; and   a digital weighting factor calculator receiving the error signal output from the power spectrum estimator and computing the digital weighting factor values therefrom.   
   
   
       10 . The equalizer according to  claim 9 , wherein the power spectrum estimator comprises:
 a pulse extraction logic circuit that compares a input signal with a delayed version of the input signal to produce an output signal containing extracted pulses;   an averaging circuit receiving the output pulse and producing therefrom an averaged signal representing the averaged value of the output signal;   a subtracter that subtracts a reference signal from the averaged signal to produce a difference signal; and   an absolute value circuit that converts the difference signal to the error signal by taking the absolute value of the difference signal.   
   
   
       11 . The equalizer according to  claim 10 , wherein the reference signal comprises a random digital signal passed through a pulse extraction logic circuit and an averaging circuit. 
   
   
       12 . The equalizer according to  claim 10 , wherein the power spectrum estimator estimates the power spectrum using pulse extraction logic circuits that extract pulses of at least one of: one, two and three different pulse widths. 
   
   
       13 . The equalizer according to  claim 9 , wherein the averaging circuit comprises a low pass filter.