Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics

Abstract

Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.

What is claimed is: 
     
         1 . An intermediate semiconductor device comprising:
 a substrate with at least one fin comprising at least one channel;   at least one gate over the at least one channel;   at least one hard-mask over the at least one gate; and   at least one spacer disposed over the at least one gate and at least one hard-mask.   
     
     
         2 . The device of  claim 1 , further comprising:
 at least one shallow trench isolation region in the substrate.   
     
     
         3 . The device of  claim 2 , further comprising:
 at least one recess in the substrate.   
     
     
         4 . The device of  claim 3 , further comprising:
 a barrier dielectric layer in a bottom of the at least one recess.   
     
     
         5 . The device of  claim 4 , wherein a top of the barrier dielectric layer is positioned below an exposed active region of the at least one fin. 
     
     
         6 . The device of  claim 5 , further comprising:
 at least one epitaxial growth layer over the barrier dielectric layer.   
     
     
         7 . The device of  claim 6 , wherein the at least one epitaxial growth layer comprises:
 a first epitaxial growth layer in at least one first recess; and   a second epitaxial growth layer in at least one second recess.   
     
     
         8 . The device of  claim 7 , wherein the first epitaxial growth layer comprises an nFET material and the second epitaxial growth layer comprises a pFET material. 
     
     
         9 . The device of  claim 8 , wherein the nFET material is SiGe and the pFET material is Si:C. 
     
     
         10 . The device of  claim 6 , wherein the at least one epitaxial growth layer is Si.