Fabricating fin structures with doped middle portions

Abstract

Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

1 - 20 . (canceled) 
     
     
         21 . A method comprising:
 fabricating at least one fin structure, the at least one fin structure comprising a doped middle portion separating an upper undoped portion from a lower undoped portion, and the fabricating comprising:
 providing an isolation layer in contact with the lower portion of the at least one fin structure; 
 forming a doping layer above the isolation layer and in contact with the at least one fin structure; and 
 diffusing dopants from the doping layer into the at least one fin structure to form the doped middle portion thereof and inhibiting diffusion of dopants into the upper undoped portion and lower doped portion 
   
     
     
         22 . The method of  claim 21 , wherein the method comprises:
 fabricating a transistor having a channel region, the channel region comprising the upper portion of the at least one fin structure, wherein the doped middle portion of the at least one fin structure reduces leakage current between the source region and the drain region of the transistor.   
     
     
         23 . The method of  claim 21 , wherein the at least one fin structure comprises at least one first fin structure and at least one second fin structure, and the fabricating comprises:
 forming the doping layer with a first thickness in contact with the at least one first fin structure and a second thickness in contact with the at least one second fin structure; and   annealing the doping layer to form a first doped middle portion of the at least one first fin structure with the first thickness and a second doped middle portion of the at least one second fin structure with the second thickness, wherein the first thickness and the second thickness are different thicknesses.   
     
     
         24 . The method of  claim 23 , wherein the method comprises:
 fabricating an integrated circuit comprising a first transistor and a second transistor, the first transistor comprising the at least one first fin structure and the second transistor comprising the at least one second fin structure, and the first thickness of the first doped middle portion the first transistor having a first threshold voltage characteristic and the second thickness of the second doped middle portion facilitates the second transistor having a second threshold voltage characteristic, wherein the first threshold voltage characteristic and the second threshold voltage characteristic are different threshold voltage characteristics.   
     
     
         25 . The method of  claim 21 , wherein the at least one fin structure comprises at least one first fin structure and at least one second fin structure, and the fabricating comprises:
 forming the doping layer with first dopants in contact with the at least one first fin structure and second dopants in contact with the at least one second fin structure, wherein the first dopants and second dopants are different dopants; and   annealing the doping layer to form a first doped middle portion of the at least one first fin structure having the first dopants and a second doped middle portion of the at least one second fin structure having the second dopants.   
     
     
         26 . The method of  claim 25 , wherein the first dopants comprise n-type dopants and the second dopants comprise p-type dopants, and the method comprises:
 fabricating an integrated circuit comprising a p-type transistor and an n-type transistor, the p-type transistor comprising the at least one first fin structure and the n-type transistor comprising the at least one second fin structure.   
     
     
         27 . The method of  claim 21 , wherein the at least one fin structure comprises at least one first fin structure and at least one second fin structure, and the fabricating comprises:
 forming the doping layer with a first initial dopant concentration in contact with the at least one first fin structure and a second initial dopant concentration in contact with the at least one second fin structure, wherein the first initial dopant concentration and the second initial dopant concentration are different concentrations; and   annealing the doping layer to form a first middle portion of the at least one first fin structure with a first final dopant concentration and a second middle portion of the at least one second fin structure with a second final dopant concentration, wherein the first final dopant concentration and the second final dopant concentration are different dopant concentrations.   
     
     
         28 . The method of  claim 27 , wherein the method comprises:
 fabricating an integrated circuit comprising a first transistor and a second transistor, the first transistor comprising the at least one first fin structure and the second transistor comprising the at least one second fin structure, and the first concentration of the dopants facilitates the first transistor having a first threshold voltage characteristic and the second concentration of the dopants facilitates the second transistor having a second threshold voltage characteristic, wherein the first threshold voltage characteristic and the second threshold voltage characteristic are different threshold voltage characteristics.   
     
     
         29 . The method of  claim 21 , wherein the fabricating comprises:
 providing a substrate underlying the at least one fin structure; and   implanting other dopants into the substrate to form a substrate well region thereof, wherein the other dopants and the dopants of the doping layer are different dopants.   
     
     
         30 . The method of  claim 21 , further comprising:
 forming a conformal gate structure over the isolation material and in contact with the at least one fin structure, wherein the isolation material facilitates aligning the conformal gate structure in contact with the upper portion of the at least one fin structure but not in contact with the doped middle portion thereof.   
     
     
         31 . The method of  claim 21 , further comprising annealing the doping layer to facilitate diffusing dopants from the doping layer into the middle portion of the at least one fin structure. 
     
     
         32 . The method of  claim 21 , wherein forming the doping layer comprises epitaxially forming a material over the at least one fin structure to form the doping layer. 
     
     
         33 . The method of  claim 21 , wherein forming the doping layer comprises providing a material, and concurrently therewith doping the material with the dopants, to form the doping layer. 
     
     
         34 . A semiconductor structure comprising:
 a FinFET having at least one fin structure wherein a middle portion of the fin structure is doped, and wherein an upper portion of the fin structure above the middle portion and a lower portion of the fin structure below the middle portion are both undoped.   
     
     
         35 . The structure of  claim 34  wherein the structure comprises a channel region within the upper portion of the at least one fin structure. 
     
     
         36 . The structure of  claim 35  wherein middle portion of the at least one fin structure reduces leakage current between a source region and drain region of a transistor. 
     
     
         37 . The structure of  claim 36  wherein the structure comprises:
 an integrated circuit comprising a first transistor and a second transistor, the first transistor comprising the at least one first fin structure and the second transistor comprising the at least one second fin structure, and the first thickness of the first doped middle portion the first transistor having a first threshold voltage characteristic and the second thickness of the second doped middle portion facilitates the second transistor having a second threshold voltage characteristic, wherein the first threshold voltage characteristic and the second threshold voltage characteristic are different threshold voltage characteristics. 
 
     
     
         38 . The structure of  claim 36  further comprising:
 a substrate underlying the at least one fin structure; and 
 implanting other dopants into the substrate to form a substrate well region thereof, wherein the other dopants and the dopants of the doping layer are different dopants. 
 
     
     
         39 . The structure of  claim 36  wherein dopants within the middle portion comprise at least one of boron, phosphorous or arsenic. 
     
     
         40 . The structure of  claim 34  wherein the middle portion of the fin structure is oxidized.