Inventor · disambiguated record
Jody A. Fronheiser
Also filed as: FRONHEISER JODY · FRONHEISER JODY A · FRONHEISER JODY ALAN
49 granted patents·20 pending applications·348 citations·filing 2005–2024
98Inventor score
Top patents by PatentIndex Score
69 records- 0198US9343300B1Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel regionGLOBALFOUNDRIES INC·Filed 2015·Granted May 17, 2016·45 cites·18 claims
- 0297US9165837B1Method to form defect free replacement fins by H2 annealGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 20, 2015·35 cites·20 claims
- 0396US9362405B1Channel cladding last process flow for forming a channel region on a FinFET deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 7, 2016·20 cites·19 claims
- 0496US8728885B1Methods of forming a three-dimensional semiconductor device with a nanowire channel structureGLOBALFOUNDRIES INC·Filed 2012·Granted May 20, 2014·31 cites·24 claims
- 0595US7850941B2Nanostructure arrays and methods for forming sameGEN ELECTRIC·Filed 2006·Granted Dec 14, 2010·25 cites·19 claims
- 0694US8673718B2Methods of forming FinFET devices with alternative channel materialsMASZARA WITOLD P·Filed 2012·Granted Mar 18, 2014·27 cites·16 claims
- 0793US9117875B2Methods of forming isolated germanium-containing fins for a FinFET semiconductor deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 25, 2015·14 cites·20 claims
- 0892US9224865B2FinFET with insulator under channelGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 29, 2015·13 cites·9 claims
- 0992US8580642B1Methods of forming FinFET devices with alternative channel materialsMASZARA WITOLD P·Filed 2012·Granted Nov 12, 2013·19 cites·21 claims
- 1091US9564486B2Self-aligned dual-height isolation for bulk FinFETIBM·Filed 2015·Granted Feb 7, 2017·7 cites·13 claims
- 1191US9236452B2Raised source/drain EPI with suppressed lateral EPI overgrowthGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·10 cites·15 claims
- 1290US8815685B2Methods for fabricating integrated circuits having confined epitaxial growth regionsGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 26, 2014·10 cites·18 claims
- 1390US7691711B2Method for fabricating silicon carbide vertical MOSFET devicesGEN ELECTRIC·Filed 2008·Granted Apr 6, 2010·19 cites·25 claims
- 1489US9716174B2Electrical isolation of FinFET active region by selective oxidation of sacrificial layerGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 25, 2017·10 cites·9 claims
- 1585US9647086B2Early PTS with buffer for channel doping controlGLOBALFOUNDRIES INC·Filed 2015·Granted May 9, 2017·5 cites·20 claims
- 1684US8853019B1Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal processGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 7, 2014·7 cites·34 claims
- 1783US9478663B2FinFET device including a uniform silicon alloy finGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 25, 2016·5 cites·20 claims
- 1883US9245980B2Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 26, 2016·6 cites·16 claims
- 1983US7595241B2Method for fabricating silicon carbide vertical MOSFET devicesGEN ELECTRIC·Filed 2006·Granted Sep 29, 2009·9 cites·19 claims
- 2081US9530869B2Methods of forming embedded source/drain regions on finFET devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 27, 2016·3 cites·22 claims
- 2180US9324618B1Methods of forming replacement fins for a FinFET deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 26, 2016·3 cites·23 claims
- 2279US9324790B2Self-aligned dual-height isolation for bulk FinFETIBM·Filed 2013·Granted Apr 26, 2016·4 cites·12 claims
- 2377US9406803B2FinFET device including a uniform silicon alloy finGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 2, 2016·2 cites·20 claims
- 2475US9882052B2Forming defect-free relaxed SiGe finsGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 30, 2018·2 cites·15 claims
- 2575US9508848B1Methods of forming strained channel regions on FinFET devices by performing a heating process on a heat-expandable materialGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 29, 2016·2 cites·21 claims
- 2675US9502507B1Methods of forming strained channel regions on FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 22, 2016·2 cites·25 claims
- 2774US10032912B2Semiconductor integrated structure having an epitaxial SiGe layer extending from silicon-containing regions formed between segments of oxide regionsST MICROELECTRONICS INC·Filed 2014·Granted Jul 24, 2018·2 cites·19 claims
- 2873US9240342B2Methods of forming replacement fins for a FinFET semiconductor device by performing a replacement growth processGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 19, 2016·2 cites·12 claims
- 2972US7906427B2Dimension profiling of SiC devicesGEN ELECTRIC·Filed 2008·Granted Mar 15, 2011·3 cites·16 claims
- 3070US9508853B2Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel regionGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 29, 2016·1 cites·18 claims
- 3168US9614058B2Methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 4, 2017·1 cites·18 claims
- 3267US10170616B2Methods of forming a vertical transistor deviceGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 1, 2019·1 cites·17 claims
- 3366US9165767B2Semiconductor structure with increased space and volume between shaped epitaxial structuresGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 20, 2015·1 cites·14 claims
- 3464US9190411B2Retrograde doped layer for device isolationGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 17, 2015·1 cites·20 claims
- 3563US9881830B2Electrically insulated fin structure(s) with alternative channel materials and fabrication methodsGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 30, 2018·1 cites·14 claims
- 3659US2024136229A1Channel uniformity horizontal gate all around deviceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3759US2024274724A1Uniform sige channel in nanosheet architectureAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 3856US11417759B2Semiconductor device and method for reduced bias threshold instabilityGEN ELECTRIC·Filed 2019·Granted Aug 16, 2022·0 cites·18 claims
- 3955US2024014214A1INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGYAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 4054US10643894B2Surface area and Schottky barrier height engineering for contact trench epitaxyIBM·Filed 2017·Granted May 5, 2020·0 cites·16 claims
- 4152US10163677B2Electrically insulated fin structure(s) with alternative channel materials and fabrication methodsGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 25, 2018·0 cites·12 claims
- 4251US2009267141A1Method for fabricating silicon carbide vertical mosfet devicesGEN ELECTRIC·Filed 2009·Application pending·0 cites
- 4350US10680065B2Field-effect transistors with a grown silicon-germanium channelGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 9, 2020·0 cites·8 claims
- 4450US10643893B2Surface area and Schottky barrier height engineering for contact trench epitaxyIBM·Filed 2016·Granted May 5, 2020·0 cites·20 claims
- 4550US2018130656A1FORMING DEFECT-FREE RELAXED SiGe FINSGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 4649US9455140B2Methods of forming doped epitaxial SiGe material on semiconductor devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 27, 2016·0 cites·27 claims
- 4748US2016035728A1Retrograde doped layer for device isolationGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 4848US2016064250A1Methods of forming metastable replacement fins for a finfet semiconductor device by performing a replacement growth processGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 4948US2016056238A1Raised source/drain epi with suppressed lateral epi overgrowthGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 5048US2014264488A1Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
Showing the top 50 of 69 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →