Inventor · disambiguated record
Norihito Masuda
Also filed as: MASUDA NORIHITO
20 granted patents·4 pending applications·378 citations·filing 2005–2023
94Inventor score
Top patents by PatentIndex Score
24 records- 0198US9224717B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2014·Granted Dec 29, 2015·76 cites·20 claims
- 0298US9093435B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2013·Granted Jul 28, 2015·68 cites·23 claims
- 0398US8618659B2Package-on-package assembly with wire bonds to encapsulation surfaceSATO HIROAKI·Filed 2012·Granted Dec 31, 2013·147 cites·38 claims
- 0497US11830845B2Package-on-package assembly with wire bonds to encapsulation surfaceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Nov 28, 2023·4 cites·19 claims
- 0597US8487421B2Microelectronic package with stacked microelectronic elements and method for manufacture thereofSATO HIROAKI·Filed 2011·Granted Jul 16, 2013·38 cites·36 claims
- 0692US9137903B2Semiconductor chip assembly and method for making sameKANG TECK-GYU·Filed 2011·Granted Sep 15, 2015·13 cites·20 claims
- 0791US10062661B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2017·Granted Aug 28, 2018·5 cites·14 claims
- 0885US11424211B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA LLC·Filed 2020·Granted Aug 23, 2022·1 cites·29 claims
- 0983US7923828B2Structure and method of making interconnect element, and multilayer wiring board including the interconnect elementTESSERA INTERCONNECT MATERIALS INC·Filed 2005·Granted Apr 12, 2011·16 cites·12 claims
- 1077US10593643B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2018·Granted Mar 17, 2020·1 cites·14 claims
- 1175US8890304B2Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer materialSATO HIROAKI·Filed 2011·Granted Nov 18, 2014·3 cites·21 claims
- 1272US12494453B2Package-on-package assembly with wire bonds to encapsulation surfaceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Dec 9, 2025·0 cites·16 claims
- 1372US10833044B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2020·Granted Nov 10, 2020·0 cites·18 claims
- 1470US9691731B2Package-on-package assembly with wire bonds to encapsulation surfaceTESSERA INC·Filed 2015·Granted Jun 27, 2017·1 cites·20 claims
- 1566US8859420B2Structure and method of making interconnect element, and multilayer wiring board including the interconnect elementENDO KIMITAKA·Filed 2011·Granted Oct 14, 2014·2 cites·19 claims
- 1665US8957520B2Microelectronic assembly comprising dielectric structures with different young modulus and having reduced mechanical stresses between the device terminals and external contactsSATO HIROAKI·Filed 2011·Granted Feb 17, 2015·2 cites·40 claims
- 1760US8525338B2Chip with sintered connections to packageSATO HIROAKI·Filed 2011·Granted Sep 3, 2013·1 cites·22 claims
- 1857US9337165B2Method for manufacturing a fan-out WLP with packageTESSERA INC·Filed 2014·Granted May 10, 2016·0 cites·17 claims
- 1952US9716075B2Semiconductor chip assembly and method for making sameTESSERA INC·Filed 2015·Granted Jul 25, 2017·0 cites·11 claims
- 2052US8786070B2Microelectronic package with stacked microelectronic elements and method for manufacture thereofTESSERA INC·Filed 2013·Granted Jul 22, 2014·0 cites·4 claims
- 2152US2017309593A1Semiconductor chip assembly and method for making sameTESSERA INC·Filed 2017·Application pending·0 cites
- 2249US2016254247A1Fan-out WLP with packageTESSERA INC·Filed 2016·Application pending·0 cites
- 2345US2013037312A1High density trace formation method by laser ablationINVENSAS CORP·Filed 2011·Application pending·0 cites
- 2438US2012286416A1Semiconductor chip package assembly and method for making sameSATO HIROAKI·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →