Fan-out WLP with package

Abstract

Described herein are microelectronic packages and methods of making such packages. Consistent with an example embodiment, the package includes a microelectronic unit. Conductive traces are disposed on a surface of the microelectronic unit. The package also includes a substrate with first and second opposed surfaces. The first surface faces the surface of and is in contact with the microelectronic unit; the second surface has a plurality of terminals configured for electrical connection with a least one external component. The substrate has conductive interconnects that include masses of conductive material joined to the conductive traces and electrically connected with the terminals. Conductive material passes from the second surface to the first surface and contacts the conductive traces and the terminals.

1 . A microelectronic package, comprising:
 a microelectronic unit;   conductive traces disposed on a surface of the microelectronic unit; and   a substrate having first and second opposed surfaces, the first surface facing the surface of and in contact with the microelectronic unit, the second surface having a plurality of terminals thereon configured for electrical connection with a least one external component, the substrate having conductive interconnects, the conductive interconnects including masses of conductive material joined to the conductive traces and electrically connected with the terminals, wherein the conductive material passes from the second surface to the first surface and contacting the conductive traces and the terminals.   
     
     
         2 . The microelectronic package of  claim 1 , wherein the conductive material comprises a high melting point material, a low melting point material, and a polymer. 
     
     
         3 . The microelectronic package of  claim 1 , wherein the conductive interconnects extend in a direction between the first and second surfaces of the substrate. 
     
     
         4 . The microelectronic package of  claim 1 , wherein the terminals include a solid metal post portion that extends at least partially through the substrate to an end surface located between the first and second surfaces of the substrate, and wherein the conductive interconnects are joined with the end surfaces. 
     
     
         5 . The microelectronic package of  claim 1 , wherein the substrate includes a compliant dielectric layer. 
     
     
         6 . The microelectronic package of  claim 1 , further including,
 a dielectric material having a first surface substantially flush with the surface of the microelectronic element; and   an underfill layer between a common surface including the surface of the microelectronic element and the first surface of the dielectric layer and the first surface of the substrate.   
     
     
         7 . The microelectronic package of  claim 6 , further including conductive redistribution contacts connected with the conductive traces, at least some of which are disposed at the first surface of the dielectric material. 
     
     
         8 . A microelectronic assembly, including the microelectronic package of  claim 1 ;
 a circuit panel having a plurality of circuit contacts thereon; and   conductive masses joining the terminals of the substrate with respective ones of the circuit contacts.   
     
     
         9 . The microelectronic package of  claim 1 , wherein the microelectronic element is a first microelectronic element, the microelectronic unit further including a second microelectronic element having a front face, edges bounding the front face, and contacts on the first face, wherein the conductive traces extend from contact on each of the first and second microelectronic elements. 
     
     
         10 . The microelectronic package of  claim 1 , wherein the terminals of the substrate are first terminals electrically interconnected with the contacts of the first microelectronic element, the substrate further including second terminals electrically interconnected with the contacts of the second microelectronic element, and wherein the conductive elements of the substrate are conductive traces that extend along the second surface of the substrate between at least some of the first terminals and respective ones of at least some of the second terminals. 
     
     
         11 . A method for making a microelectronic package, comprising:
 providing a microelectronic unit, wherein conductive traces are disposed on a surface of the microelectronic unit; and   electrically connecting a substrate to the microelectronic unit,
 wherein the substrate includes first and second opposed surfaces, the first surface facing the surface of and in contact with the microelectronic unit, the second surface having a plurality of terminals thereon configured for electrical connection with a least one external component, the substrate having conductive interconnects, the conductive interconnects including masses of conductive material passing from the second surface to the first surface and contacting the conductive traces. 
   
     
     
         12 . The method of  claim 11 , wherein the microelectronic unit includes conductive redistribution contacts connected with the conductive traces, at least some of which are disposed at the first surface of the microelectronic unit and electrically contacting at least one of the conductive interconnects on the first surface of the substrate. 
     
     
         13 . The method of  claim 11 , wherein the at least one opening includes a plurality of openings and the step of electrically connecting includes forming the plurality of openings after assembling the microelectronic unit with the substrate and then depositing the conductive material within the plurality of openings. 
     
     
         14 . The method of  claim 11 , further comprising selecting the conductive material such that the selected conductive material is comprised of a high melting point material, a low melting point material, and a polymer. 
     
     
         15 . The method of  claim 11 , further comprising heating the microelectronic unit and the substrate to a sintering temperature. 
     
     
         16 . The method of  claim 14 , further comprising fusing the high and low melting point materials together and forming an intermetallic material therebetween. 
     
     
         17 . The method of  claim 12 , wherein the step of electrically connecting is performed in a low-pressure environment. 
     
     
         18 . The method of  claim 16 , wherein the low-pressure environment is a partial vacuum. 
     
     
         19 . The method of  claim 14 , further comprising depositing the conductive material into the at least one opening and curing the conductive material so that the material is flowable and retains at least a portion of its shape when deposited.