Inventor · disambiguated record
Eric C. Harley
Also filed as: HARLEY ERIC · HARLEY ERIC C · HARLEY ERIC C T
29 granted patents·6 pending applications·127 citations·filing 2008–2019
96Inventor score
Top patents by PatentIndex Score
35 records- 0194US9577100B2FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regionsGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 21, 2017·17 cites·13 claims
- 0294US9287264B1Epitaxially grown silicon germanium channel FinFET with silicon underlayerGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 15, 2016·15 cites·12 claims
- 0394US8492234B2Field effect transistor deviceCHAN KEVIN K·Filed 2010·Granted Jul 23, 2013·16 cites·12 claims
- 0492US8361859B2Stressed transistor with improved metastabilityIBM·Filed 2010·Granted Jan 29, 2013·13 cites·15 claims
- 0587US9123826B1Single crystal source-drain merged by polycrystalline materialIBM·Filed 2014·Granted Sep 1, 2015·8 cites·20 claims
- 0685US9246003B2FINFET structures with fins recessed beneath the gateGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 26, 2016·7 cites·18 claims
- 0783US10243077B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2017·Granted Mar 26, 2019·2 cites·10 claims
- 0883US8232186B2Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structureHARLEY ERIC C T·Filed 2008·Granted Jul 31, 2012·13 cites·16 claims
- 0980US9917190B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2015·Granted Mar 13, 2018·2 cites·7 claims
- 1080US9412843B2Method for embedded diamond-shaped stress elementIBM·Filed 2014·Granted Aug 9, 2016·4 cites·20 claims
- 1180US9312364B2finFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2014·Granted Apr 12, 2016·3 cites·11 claims
- 1280US7769134B1Measuring strain of epitaxial films using micro x-ray diffraction for in-line metrologyIBM·Filed 2009·Granted Aug 3, 2010·7 cites·25 claims
- 1378US9318608B1Uniform junction formation in FinFETsIBM·Filed 2014·Granted Apr 19, 2016·3 cites·5 claims
- 1478US8618617B2Field effect transistor deviceIBM·Filed 2013·Granted Dec 31, 2013·3 cites·9 claims
- 1576US9577099B2Diamond shaped source drain epitaxy with underlying buffer layerGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 21, 2017·2 cites·17 claims
- 1672US9236477B2Graphene transistor with a sublithographic channel widthGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·2 cites·20 claims
- 1769US9466616B2Uniform junction formation in FinFETsGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 11, 2016·1 cites·5 claims
- 1867US11081583B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2019·Granted Aug 3, 2021·0 cites·10 claims
- 1967US9536985B2Epitaxial growth of material on source/drain regions of FinFET structureGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 3, 2017·2 cites·11 claims
- 2066US8987093B2Multigate finFETs with epitaxially-grown merged source/drainsIBM·Filed 2012·Granted Mar 24, 2015·2 cites·13 claims
- 2165US8080451B2Fabricating semiconductor structuresADAM THOMAS N·Filed 2010·Granted Dec 20, 2011·1 cites·19 claims
- 2264US9219114B2Partial FIN on oxide for improved electrical isolation of raised active regionsGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 22, 2015·1 cites·9 claims
- 2364US7687804B2Method for fabricating a semiconductor structures and structures thereofIBM·Filed 2008·Granted Mar 30, 2010·1 cites·12 claims
- 2462US9752251B2Self-limiting selective epitaxy process for preventing merger of semiconductor finsIBM·Filed 2013·Granted Sep 5, 2017·1 cites·25 claims
- 2561US7955936B2Semiconductor fabrication process including an SiGe rework methodCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Jun 7, 2011·1 cites·19 claims
- 2657US10615279B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2016·Granted Apr 7, 2020·0 cites·11 claims
- 2753US9390884B2Method of inspecting a semiconductor substrateGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 12, 2016·0 cites·7 claims
- 2852US2014159161A1Measurement of cmos device channel strain by x-ray diffractionIBM·Filed 2014·Application pending·0 cites
- 2948US2013134444A1Stressed transistor with improved metastabilityIBM·Filed 2013·Application pending·0 cites
- 3048US2016163707A1Epitaxially grown silicon germanium channel finfet with silicon underlayerGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 3147US8716037B2Measurement of CMOS device channel strain by X-ray diffractionADAM THOMAS N·Filed 2010·Granted May 6, 2014·0 cites·15 claims
- 3247US2016079397A1Partial fin on oxide for improved electrical isolation of raised active regionsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 3342US2012228716A1METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTUREHARLEY ERIC C T·Filed 2012·Application pending·0 cites
- 3438US2012190216A1Annealing techniques for high performance complementary metal oxide semiconductor (cmos) device fabricationCHAN KEVIN K·Filed 2011·Application pending·0 cites
- 3537US8084788B2Method of forming source and drain of a field-effect-transistor and structure thereofHOLT JUDSON ROBERT·Filed 2008·Granted Dec 27, 2011·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →