Partial fin on oxide for improved electrical isolation of raised active regions

Abstract

A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

1 .- 10 . (canceled) 
     
     
         11 . A method of forming a semiconductor structure comprising:
 providing a structure including a semiconductor material layer, an insulator layer contacting a portion of a top surface of said semiconductor material layer, a semiconductor fin overlying a portion of said insulator layer, a gate stack straddling said semiconductor fin, and a gate spacer that is present around said gate stack;   removing physically exposed portions of said semiconductor fin, wherein a remaining portion of said semiconductor fin has a first end surface that is vertically coincident with a first outer sidewall of said gate spacer and a second end surface that is vertically coincident with a second outer sidewall of said gate spacer; and   forming a first opening and a second opening extending to said semiconductor material layer through said insulator layer, wherein a lateral offset distance between a bottom periphery of said first opening and said first end surface is the same as a lateral offset distance between a bottom periphery of said second opening and said second end surface.   
     
     
         12 . The method of  claim 11 , wherein said structure is provided by:
 forming a vertical stack, from bottom to top, of a disposable material layer and said semiconductor fin on said semiconductor material layer;   forming said gate stack over said vertical stack; and   removing said disposable material layer from underneath said semiconductor fin while said semiconductor fin is mechanically supported by said gate stack.   
     
     
         13 . The method of  claim 11 , wherein said first opening and said second opening is formed employing said gate spacer and said gate stack as an etch mask. 
     
     
         14 . The method of  claim 11 , wherein an edge at which said first opening adjoins a top surface of said insulator layer is vertically coincident with said first outer sidewall, and an edge at which said second opening adjoins said top surface of said insulator layer is vertically coincident with said second outer sidewall. 
     
     
         15 . The method of  claim 11 , wherein said first opening and said second opening are formed with a taper. 
     
     
         16 . The method of  claim 11 , further comprising:
 forming a disposable spacer around said gate spacer, wherein said first opening and said second opening are formed by an etch process employing said gate stack, said gate spacer, and said disposable spacer as an etch mask; and   removing said disposable spacer.   
     
     
         17 . The method of  claim 16 , wherein sidewalls of said first opening and said second opening are substantially vertical. 
     
     
         18 . The method of  claim 11 , further comprising:
 forming a source region on a first portion of said semiconductor material layer underneath said first opening and on said first end surface; and   forming a drain region on a second portion of said second semiconductor material layer underneath said second opening and on said second end surface.   
     
     
         19 . The method of  claim 18 , wherein each of said semiconductor fin and said semiconductor material layer is single crystalline, and each of said source region and said drain region includes a portion that is epitaxially aligned to said semiconductor material layer and another portion that is epitaxially aligned to said semiconductor fin. 
     
     
         20 . The method of  claim 11 , further comprising:
 selectively depositing a semiconductor material on said first portion of said semiconductor material layer, said second portion of said semiconductor material layer, said first end surface, and said second end surface; and   patterning said deposited semiconductor material, wherein a first remaining portion of said deposited semiconductor material is said source region, a second remaining portion of said deposited semiconductor material is said drain region, and portions of said top surface of said semiconductor material layer are physically exposed after patterning said deposited semiconductor material.   
     
     
         21 . The method of  claim 15 , wherein said first opening and said second opening are formed with a tapered surface extending from a top surface of said insulator layer to an interface between said insulator layer and said semiconductor material layer. 
     
     
         22 . The method of  claim 11 , further comprising forming a photoresist layer covering end portions of said gate stack but not said semiconductor fin, wherein said first opening and said second opening is formed employing said gate spacer, said gate stack, and said photoresist layer as an etch mask. 
     
     
         23 . The method of  claim 16 , wherein sidewalls of said first opening and said second opening are substantially vertical.