US2012228716A1PendingUtilityA1

METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE

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Assignee: HARLEY ERIC C TPriority: May 29, 2008Filed: May 23, 2012Published: Sep 13, 2012
Est. expiryMay 29, 2028(~1.8 yrs left)· nominal 20-yr term from priority
Inventors:Eric C. HarleyJudson R. HoltDominic J. SchepisMichael D. SteigerwaltLinda BlackRick Carter
H10D 62/832H10D 62/021H10D 84/0167H10D 30/797H10D 30/751H10D 84/038H10D 84/017
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Claims

Abstract

A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.

Claims

exact text as granted — not AI-modified
1 . A structure comprising:
 an NFET having an embedded silicon germanium (SiGe) plug in a channel thereof;   a PFET having a SiGe channel; and   a trench isolation between the NFET and the PFET,   wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.   
     
     
         2 . The structure of  claim 1 , wherein the embedded SiGe plug and the SiGe channel are part of a single layer of SiGe. 
     
     
         3 . A structure comprising:
 an NFET having an embedded silicon germanium (SiGe) plug in a channel thereof;   a PFET having a SiGe channel, wherein a height of the NFET and a height of the PFET are different; and   a trench isolation between the NFET and the PFET,   wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.   
     
     
         4 . The structure of  claim 3 , wherein the embedded SiGe plug and the SiGe channel are part of a single layer of SiGe. 
     
     
         5 . The structure of  claim 3 , wherein the height of the NFET and the height of the PFET differ by between about 10 nm and about 20 nm. 
     
     
         6 . An integrated circuit chip, comprising:
 at least one structure, including:
 an NFET having an embedded silicon germanium (SiGe) plug in a channel thereof; 
 a PFET having a SiGe channel; and 
 a trench isolation between the NFET and the PFET, 
 wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects. 
   
     
     
         7 . The integrated circuit chip of  claim 6 , wherein the embedded SiGe plug and the SiGe channel are part of a single layer of SiGe. 
     
     
         8 . The integrated circuit chip of  claim 6 , wherein a height of the NFET and a height of the PFET are different. 
     
     
         9 . The integrated circuit chip of  claim 8 , wherein the height of the NFET and the height of the PFET differ by between about 10 nm and about 20 nm.

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