Measurement of cmos device channel strain by x-ray diffraction

Abstract

A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a periodic array of unit structures on a substrate, wherein each of said unit structures includes a single crystalline strained material region, at least one stress-generating material region that applies stress to said single crystalline strained material region, a single crystalline unstrained material region, wherein said periodic array of unit structures is not contacted by any structure configured to apply electrical current through any portion of said periodic array of unit structures; and   a semiconductor device on said substrate including another single crystalline strained material region, and at least another stress-generating material region that applies stress to said other single crystalline strained material region, wherein said semiconductor device is configured to flow electrical current through said single crystalline strained material region.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said single crystalline strained material region comprises a first single crystalline semiconductor material, and said single crystalline unstrained material region comprises said first single crystalline semiconductor material. 
     
     
         3 . The semiconductor structure of  claim 2 , further comprising at least one shallow trench isolation region, wherein said at least one shallow trench isolation region vertically extends from a topmost surface of the single crystalline semiconductor material to a bottommost surface of the single crystalline semiconductor material. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein said at least one stress-generating material region includes a second single crystalline semiconductor material that is different from said first single crystalline semiconductor material. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein said second single crystalline semiconductor material in said at least one stress-generating material region is epitaxially aligned to said first single crystalline semiconductor material in said single crystalline strained material region and to said first single crystalline semiconductor material in said single crystalline unstrained material region. 
     
     
         6 . The semiconductor structure of  claim 4 , wherein said first single crystalline semiconductor material is single crystalline silicon and said second single crystalline semiconductor material is a single crystalline alloy of silicon of at least one group IV element other than silicon. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein said at least one group IV element other than silicon is selected from germanium and carbon. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein said other single crystalline strained material region has a same material as said single crystalline strained material region and said at least another stress-generating material region has the same material as said at least one stress-generating material region. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein each of said unit structures includes a stack structure including a dielectric material portion and a conductive material portion, wherein said stack structure contacts and overlies said single crystalline strained material region, and said conductive material portion is encapsulated by said dielectric material portion and at least one dielectric material layer without contacting a conductive structure. 
     
     
         10 . The semiconductor structure of  claim 8 , further comprising at least one contact via structure, wherein said at least one contact via structure contacts said dielectric material portion. 
     
     
         11 . The semiconductor structure of  claim 1 , further comprising another periodic array of second unit structures on said substrate, said second unit structures differ from said unit structures by composition or volume of an element corresponding to said single crystalline strained material region, said at least one stress-generating material region, or said single crystalline unstrained material region. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein said at least one stress-generating material region comprises a semiconductor alloy, wherein said semiconductor alloy has a different lattice constant than that of the single crystalline semiconductor layer. 
     
     
         13 . The semiconductor structure of  claim 1 , wherein said periodic array of unit structures have one-directional periodicity. 
     
     
         14 . The semiconductor structure of  claim 1 , wherein said at least one stress-generating material region and said at least another stress-generating material region have different widths. 
     
     
         15 . The semiconductor structure of  claim 1 , wherein said single crystalline strained material region and said other single crystalline strained material region have different widths. 
     
     
         16 . The semiconductor structure of  claim 1 , further comprising a field effect transistor, wherein said field effect transistor comprises a gate dielectric material portion, and a gate electrode. 
     
     
         17 . The semiconductor structure of  claim 16 , wherein said field effect transistor further comprises a single crystalline semiconductor layer. 
     
     
         18 . The semiconductor structure of  claim 16 , wherein said field effect transistor further comprises embedded source and drain regions.