Inventor · disambiguated record
Roger A. Quon
Also filed as: QUON ROGER A · QUON ROGER ALLAN · SABLINSKI WILLIAM E
53 granted patents·16 pending applications·274 citations·filing 2003–2024
98Inventor score
Top patents by PatentIndex Score
69 records- 0198US9934970B1Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2017·Granted Apr 3, 2018·22 cites·13 claims
- 0298US9761655B1Stacked planar capacitors with scaled EOTIBM·Filed 2016·Granted Sep 12, 2017·36 cites·20 claims
- 0397US9991156B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2016·Granted Jun 5, 2018·15 cites·6 claims
- 0497US9859218B1Selective surface modification of interconnect structuresIBM·Filed 2016·Granted Jan 2, 2018·16 cites·11 claims
- 0597US9786603B1Surface nitridation in metal interconnectsIBM·Filed 2016·Granted Oct 10, 2017·14 cites·13 claims
- 0696US9779944B1Method and structure for cut material selectionIBM·Filed 2016·Granted Oct 3, 2017·17 cites·19 claims
- 0795US9780035B1Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnectsIBM·Filed 2016·Granted Oct 3, 2017·10 cites·25 claims
- 0893US10529569B2Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2018·Granted Jan 7, 2020·5 cites·11 claims
- 0992US10699945B2Back end of line integration for interconnectsIBM·Filed 2018·Granted Jun 30, 2020·5 cites·16 claims
- 1092US9607886B1Self aligned conductive lines with relaxed overlayIBM·Filed 2016·Granted Mar 28, 2017·6 cites·20 claims
- 1191US9899317B1Nitridization for semiconductor structuresIBM·Filed 2016·Granted Feb 20, 2018·8 cites·18 claims
- 1291US8574950B2Electrically contactable grids manufactureCLEVENGER LAWRENCE A·Filed 2010·Granted Nov 5, 2013·7 cites·18 claims
- 1389US9786554B1Self aligned conductive linesIBM·Filed 2016·Granted Oct 10, 2017·5 cites·7 claims
- 1489US7629264B2Structure and method for hybrid tungsten copper metal contactIBM·Filed 2008·Granted Dec 8, 2009·18 cites·19 claims
- 1589US2025062126A1Self aligned pattern formation post spacer etchback in tight pitch configurationsTESSERA LLC·Filed 2024·Application pending·0 cites
- 1688US11670510B2Self aligned pattern formation post spacer etchback in tight pitch configurationsTESSERA LLC·Filed 2021·Granted Jun 6, 2023·1 cites·18 claims
- 1788US9773700B1Aligning conductive vias with trenchesIBM·Filed 2016·Granted Sep 26, 2017·5 cites·9 claims
- 1887US10546774B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2018·Granted Jan 28, 2020·3 cites·9 claims
- 1984US12106963B2Self aligned pattern formation post spacer etchback in tight pitch configurationsTESSERA LLC·Filed 2023·Granted Oct 1, 2024·0 cites·21 claims
- 2084US10121661B2Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2017·Granted Nov 6, 2018·2 cites·17 claims
- 2182US7144490B2Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layerIBM·Filed 2003·Granted Dec 5, 2006·14 cites·7 claims
- 2281US11133216B2Interconnect structureIBM·Filed 2018·Granted Sep 28, 2021·3 cites·14 claims
- 2378US10128147B2Interconnect structureIBM·Filed 2018·Granted Nov 13, 2018·2 cites·17 claims
- 2478US7442878B2Low stress conductive polymer bumpIBM·Filed 2006·Granted Oct 28, 2008·7 cites·16 claims
- 2577US10957583B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2019·Granted Mar 23, 2021·1 cites·19 claims
- 2676US9852946B1Self aligned conductive linesIBM·Filed 2016·Granted Dec 26, 2017·2 cites·20 claims
- 2775US10529621B2Modulating the microstructure of metallic interconnect structuresIBM·Filed 2019·Granted Jan 7, 2020·0 cites·20 claims
- 2874US8792080B2Method and system to predict lithography focus error using simulated or measured topographySAPP BRIAN CHRISTOPHER·Filed 2011·Granted Jul 29, 2014·2 cites·11 claims
- 2973US9911647B2Self aligned conductive linesIBM·Filed 2017·Granted Mar 6, 2018·1 cites·20 claims
- 3072US7473997B2Method for forming robust solder interconnect structures by reducing effects of seed layer underetchingIBM·Filed 2005·Granted Jan 6, 2009·4 cites·10 claims
- 3169US7923836B2BLM structure for application to copper padIBM·Filed 2006·Granted Apr 12, 2011·4 cites·15 claims
- 3268US7926006B2Variable fill and cheese for mitigation of BEOL topographyIBM·Filed 2007·Granted Apr 12, 2011·4 cites·16 claims
- 3367US11018007B2Self aligned pattern formation post spacer etchback in tight pitch configurationsTESSERA INC·Filed 2019·Granted May 25, 2021·0 cites·20 claims
- 3467US10249532B2Modulating the microstructure of metallic interconnect structuresIBM·Filed 2017·Granted Apr 2, 2019·0 cites·12 claims
- 3566US8802990B2Self-aligned nano-scale device with parallel plate electrodesCLEVENGER LAWRENCE A·Filed 2012·Granted Aug 12, 2014·1 cites·19 claims
- 3665US7170187B2Low stress conductive polymer bumpIBM·Filed 2004·Granted Jan 30, 2007·11 cites·5 claims
- 3764US8026166B2Interconnect structures comprising capping layers with low dielectric constants and methods of making the sameIBM·Filed 2008·Granted Sep 27, 2011·3 cites·7 claims
- 3862US10615116B2Surface nitridation in metal interconnectsIBM·Filed 2018·Granted Apr 7, 2020·0 cites·20 claims
- 3962US10395985B2Self aligned conductive lines with relaxed overlayIBM·Filed 2018·Granted Aug 27, 2019·0 cites·19 claims
- 4062US10361153B2Surface nitridation in metal interconnectsIBM·Filed 2017·Granted Jul 23, 2019·0 cites·16 claims
- 4162US6995475B2I/C chip suitable for wire bondingIBM·Filed 2003·Granted Feb 7, 2006·9 cites·3 claims
- 4261US6995084B2Method for forming robust solder interconnect structures by reducing effects of seed layer underetchingIBM·Filed 2004·Granted Feb 7, 2006·7 cites·12 claims
- 4360US10068846B2Surface nitridation in metal interconnectsIBM·Filed 2017·Granted Sep 4, 2018·0 cites·20 claims
- 4460US2014071416A1Method and system to predict lithography focus error using simulated or measured topographyIBM·Filed 2013·Application pending·0 cites
- 4560US2014075399A1Method and system to predict lithography focus error using simulated or measured topographyIBM·Filed 2013·Application pending·0 cites
- 4660US2014075396A1Method and system to predict lithography focus error using simulated or measured topographyIBM·Filed 2013·Application pending·0 cites
- 4759US2020219759A1Back end of line integration for interconnectsIBM·Filed 2020·Application pending·0 cites
- 4858US10483091B1Selective ion filtering in a multipurpose chamberIBM·Filed 2018·Granted Nov 19, 2019·0 cites·10 claims
- 4958US10134674B2Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnectsIBM·Filed 2017·Granted Nov 20, 2018·0 cites·20 claims
- 5058US10083864B2Self aligned conductive lines with relaxed overlayIBM·Filed 2017·Granted Sep 25, 2018·0 cites·11 claims
Showing the top 50 of 69 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →