Method and system to predict lithography focus error using simulated or measured topography

Abstract

A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

What is claimed is: 
     
         1 - 13 . (canceled) 
     
     
         14 . A method for predicting lithography focus error for a chip by analyzing chip topography data, comprising:
 a) computing a regression plane with a least squares fit on a subset of chip topography data;   b) computing a minimal local residual of the regression plane;   c) updating a total focus error value with the minimal local residual;   d) acquiring a new subset of chip topography data; and   repeating steps a, b, c, and d until each data point within the chip topography data is considered in at least one subset, thereby computing a focus error value for the chip; and wherein the non-volatile memory further comprises:   machine instructions, that when executed, perform the step of providing a graphical region representing a wafer representation, wherein the wafer representation comprises a plurality of exposure field images, wherein each of the exposure field images indicates different focus error ranges as represented by different indicia.   
     
     
         15 . (canceled) 
     
     
         16 . The system of  claim 20 , wherein the non-volatile memory further comprises:
 machine instructions, that when executed, perform the step of changing the size of the subset of chip topography data, and repeating steps a, b, c, and d, and identifying a subset size that results in the smallest focus error, wherein the subset size is representative of a slit size.   
     
     
         17 . The system of  claim 16 , wherein the non-volatile memory further comprises:
 machine instructions, that when executed, perform the step of changing the chip layout, receiving updated chip topography, the updated chip topography representative of the changed chip layout, and repeating steps a, b, c, and d, and identifying a chip layout that results in the smallest focus error.   
     
     
         18 . The system of  claim 20 , wherein the non-volatile memory further comprises:
 machine instructions, that when executed, perform the step of deriving the chip topography data from chip density data.   
     
     
         19 . (canceled) 
     
     
         20 . A system for predicting lithography focus error for a chip by analyzing chip topography data, comprising:
 a processor;   non-volatile memory;   wherein the processor is configured and disposed to read executable instructions from the non-volatile memory, and wherein the instructions, when executed by the processor, perform the steps of:   a) computing a focal plane that best fits a subset of chip topography data;   b) computing a minimal local residual of the focal plane;   c) updating a total focus error value with the minimal local residual;   d) acquiring a new subset of chip topography data;   repeating steps a, b, c, and d until each data point within the chip topography data is considered in at least one subset, thereby computing a focus error value for the chip; and wherein the non-volatile memory further comprises:   machine instructions, that when executed, perform the step of providing a graphical region representing a wafer representation, wherein the wafer representation comprises a plurality of exposure field images, wherein each of the exposure field images indicates different focus error ranges as represented by different indicia.