Back end of line integration for interconnects

Abstract

A semiconductor device includes one or more interconnects and one or more cap layers disposed on respective ones of the one or more interconnects. The one or more cap layers include a material that has properties permitting selective deposition on the one or more interconnects.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 one or more interconnects; and   one or more cap layers disposed on respective ones of the one or more interconnects, the one or more cap layers including a material that has properties permitting selective deposition on the one or more interconnects.   
     
     
         2 . The device of  claim 1 , wherein the one or more cap layers include cobalt (Co). 
     
     
         3 . The device of  claim 1 , wherein the one or more interconnects have an aspect ratio of less than about 2. 
     
     
         4 . The device of  claim 1 , further comprising an interlevel dielectric, wherein the one or more interconnects are disposed within the interlevel dielectric. 
     
     
         5 . The device of  claim 4 , wherein the interlevel dielectric includes an ultra low-k dielectric material. 
     
     
         6 . The device of  claim 4 , wherein the interlevel dielectric has a height below the one or more cap layers. 
     
     
         7 . The device of  claim 4 , further comprising a diffusion barrier layer disposed between the interlevel dielectric and the one or more interconnects. 
     
     
         8 . The device of  claim 7 , wherein the diffusion barrier layer includes tantalum (Ta). 
     
     
         9 . The device of  claim 1 , wherein the one or more interconnects include copper (Cu). 
     
     
         10 . A semiconductor device, comprising:
 an interlevel dielectric;   one or more interconnects disposed within the interlevel dielectric;   a diffusion barrier layer disposed between the interlevel dielectric and the one or more interconnects; and   one or more cap layers disposed on respective ones of the one or more interconnects, the one or more cap layers including a material that has properties permitting selective deposition on the one or more interconnects and not the diffusion barrier layer.   
     
     
         11 . The device of  claim 10 , wherein the one or more cap layers include cobalt (Co). 
     
     
         12 . The device of  claim 10 , wherein the one or more interconnects have an aspect ratio of less than about 2. 
     
     
         13 . The device of  claim 10 , wherein the interlevel dielectric has a height below the one or more cap layers. 
     
     
         14 . The device of  claim 10 , wherein the diffusion barrier layer includes tantalum (Ta). 
     
     
         15 . The device of  claim 10 , wherein the interlevel dielectric includes an ultra low-k dielectric material. 
     
     
         16 . The device of  claim 10 , wherein the one or more interconnects include copper (Cu). 
     
     
         17 . A semiconductor device, comprising:
 an interlevel dielectric;   one or more interconnects having an aspect ratio of less than about 2 disposed within the interlevel dielectric;   a diffusion barrier layer including tantalum (Ta) disposed between the interlevel dielectric and the one or more interconnects; and   one or more cap layers including cobalt (Co) disposed on respective ones of the one or more interconnects, the one or more cap layers including a material that has properties permitting selective deposition on the one or more interconnects and not the diffusion barrier layer.   
     
     
         18 . The device of  claim 17 , wherein the interlevel dielectric has a height below the one or more cap layers. 
     
     
         19 . The device of  claim 17 , wherein the interlevel dielectric includes an ultra low-k dielectric material. 
     
     
         20 . The device of  claim 17 , wherein the one or more interconnects include copper (Cu).