Method and system to predict lithography focus error using simulated or measured topography

Abstract

A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

What is claimed is: 
     
         1 . (canceled) 
     
     
         2 . The method of  claim 7 , further comprising:
 changing the size of the subset of chip topography data, and repeating steps a, b, c, and d, and identifying a subset size that results in the smallest focus error, wherein the subset size is representative of a slit size.   
     
     
         3 . The method of  claim 7 , further comprising:
 changing the chip layout, receiving updated chip topography, the updated chip topography representative of the changed chip layout, and repeating steps a, b, c, and d, and identifying a chip layout that results in the smallest focus error.   
     
     
         4 . (canceled) 
     
     
         5 . (canceled) 
     
     
         6 . The method of  claim 7 , further comprising:
 wherein the step of deriving a Z value based on an empirical data further comprises:   measuring topology samples and corresponding density values.   
     
     
         7 . A method for predicting lithography focus error for a chip by analyzing chip topography data, comprising:
 a) computing a focal plane that best fits a subset of the chip topography data;   b) computing a minimal local residual of the focal plane;   c) updating a total focus error value with the minimal local residual;   d) acquiring a new subset of chip topography data; and   repeating steps a, b, c, and d until each data point within the chip topography data is considered in at least one subset, thereby computing a focus error value for the chip;   deriving the chip topography data from chip density data;   wherein the density data comprises the ratio of metal to dielectric material for a region within a chip; and   deriving the chip topography data from a CMP simulation.   
     
     
         8 . The method of  claim 7 , further comprising:
 providing a graphical region representing an exposure field, wherein different focus error ranges are represented by different indicia.   
     
     
         9 . The method of  claim 8 , wherein the indicia comprise different patterns. 
     
     
         10 . The method of  claim 8 , wherein the indicia comprise different colors. 
     
     
         11 . The method of  claim 7 , further comprising:
 providing a graphical region representing a wafer representation, wherein the wafer representation comprises a plurality of exposure field images, wherein each of the exposure field images indicates different focus error ranges as represented by different indicia.   
     
     
         12 . The method of  claim 7 , wherein the subset of chip topography data comprises a synthesized topology dataset. 
     
     
         13 . The method of  claim 12 , wherein the synthesized topology dataset comprises not-a-number entries. 
     
     
         14 - 20 . (canceled)