Inventor · disambiguated record
Man Fai Ng
Also filed as: NG MAN FAI
15 granted patents·7 pending applications·70 citations·filing 1996–2024
90Inventor score
Top patents by PatentIndex Score
22 records- 0190US8518758B2ETSOI with reduced extension resistanceYANG BIN·Filed 2010·Granted Aug 27, 2013·11 cites·12 claims
- 0283US8765537B2Metal gate fill by optimizing etch in sacrificial gate profileNG MAN FAI·Filed 2012·Granted Jul 1, 2014·6 cites·20 claims
- 0380US8222093B2Methods for forming barrier regions within regions of insulating material resulting in outgassing paths from the insulating material and related devicesNG MAN FAI·Filed 2010·Granted Jul 17, 2012·5 cites·20 claims
- 0476US8329515B2eFUSE enablement with thin polysilicon or amorphous-silicon gate-stack for HKMG CMOSYANG BIN·Filed 2009·Granted Dec 11, 2012·6 cites·18 claims
- 0573US8198170B2Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor materialNG MAN FAI·Filed 2010·Granted Jun 12, 2012·3 cites·16 claims
- 0668US8124515B2Gate etch optimization through silicon dopant profile changeNG MAN FAI·Filed 2009·Granted Feb 28, 2012·2 cites·12 claims
- 0764US7763508B2Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methodsGLOBALFOUNDRIES INC·Filed 2008·Granted Jul 27, 2010·2 cites·19 claims
- 0862US8674438B2Semiconductor devices having stressor regions and related fabrication methodsGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 18, 2014·1 cites·20 claims
- 0961US8445342B2Short channel semiconductor devices with reduced halo diffusionYANG BIN·Filed 2010·Granted May 21, 2013·1 cites·10 claims
- 1057US2025300051A1Interconnect structure with reentrant via bottom sidewallINTEL CORP·Filed 2024·Application pending·0 cites
- 1152US2013320447A1Etsoi with reduced extension resistanceGLOBALFOUNDERIES INC·Filed 2013·Application pending·0 cites
- 1251US8680624B2Methods for forming barrier regions within regions of insulating material resulting in outgassing paths from the insulating material and related devicesNG MAN FAI·Filed 2012·Granted Mar 25, 2014·0 cites·11 claims
- 1351US8390042B2Gate etch optimization through silicon dopant profile changeNG MAN FAI·Filed 2012·Granted Mar 5, 2013·0 cites·8 claims
- 1451US5822698AMicrocell frequency planningNORTHERN TELECOM LTD·Filed 1996·Granted Oct 13, 1998·33 cites·8 claims
- 1548US8987110B2Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor materialNG MAN FAI·Filed 2012·Granted Mar 24, 2015·0 cites·6 claims
- 1648US2013249000A1Short channel semiconductor devices with reduced halo diffusionGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 1747US8394691B2Semiconductor devices having stressor regions and related fabrication methodsYANG BIN·Filed 2010·Granted Mar 12, 2013·0 cites·16 claims
- 1847US2016260841A1Etsoi with reduced extension resistanceGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 1945US8084828B2Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methodsPAL ROHIT·Filed 2010·Granted Dec 27, 2011·0 cites·16 claims
- 2045US2010072623A1Semiconductor device with improved contact plugs, and related fabrication methodsADVANCED MICRO DEVICES INC·Filed 2008·Application pending·0 cites
- 2142US2011241118A1Metal gate fill by optimizing etch in sacrificial gate profileGLOBALFOUNDRIES INC·Filed 2010·Application pending·0 cites
- 2241US2014183720A1Methods of manufacturing integrated circuits having a compressive nitride layerGLOBALFOUNDRIES INC·Filed 2012·Application pending·0 cites
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