US2016260841A1PendingUtilityA1

Etsoi with reduced extension resistance

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Assignee: GLOBALFOUNDRIES INCPriority: Mar 18, 2010Filed: Mar 6, 2015Published: Sep 8, 2016
Est. expiryMar 18, 2030(~3.6 yrs left)· nominal 20-yr term from priority
Inventors:Bin YangMan Fai Ng
H10W 10/181H10W 10/0145H10W 10/061H10W 10/17H10W 10/014H10P 90/1906H10D 86/215H10D 86/201H10D 86/01H10D 64/017H10D 30/6757H10D 30/6741H10D 30/0323H10D 30/0275H10D 30/60H10D 30/021H10D 30/6713H01L 27/1211H01L 29/78618
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Claims

Abstract

A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 an SOI substrate;   a gate electrode formed on the SOI substrate;   an epitaxially formed silicon-containing layer on the SOI substrate, surrounding at least a bottom portion of the gate electrode.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the SOI substrate comprises a thin silicon layer on a silicon substrate with a buried oxide layer (BOX) in between, the thin silicon layer having a thickness of about 6 nm to about 8 nm. 
     
     
         3 . The semiconductor device according to  claim 1 , further comprising:
 a first spacer on the silicon-containing layer on each side of the gate electrode; and   a source/drain region on the silicon-containing layer, adjacent each first spacer.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein the source/drain regions are raised and faceted. 
     
     
         5 . The semiconductor device according to  claim 3 , further comprising a silicide on the source/drain regions. 
     
     
         6 . The semiconductor device according to  claim 3 , further comprising a second spacer on each first spacer. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the gate electrode comprises a high-k metal gate electrode. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the silicon-containing layer comprises silicon germanium. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein the silicon germanium has a thickness of about 8 nm to about 12 nm. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein the silicon-containing layer comprises carbon doped silicon (Si:C). 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the SOI substrate comprises an ETSOI substrate. 
     
     
         12 . A semiconductor device comprising:
 a silicon substrate;   a buried oxide (BOX) layer on the silicon substrate;   a thin silicon layer on the BOX layer, the thin silicon layer having a thickness of about 6 nm to about 8 nm;   a high-k metal gate electrode formed on the thin silicon layer;   an epitaxially formed silicon-containing layer on the thin silicon layer, surrounding at least a bottom portion of the high-k metal gate electrode.   
     
     
         13 . The semiconductor device according to  claim 12 , further comprising:
 a first spacer on the silicon-containing layer on each side of the gate electrode;   a second spacer on each first spacer; and   a source/drain region on the silicon-containing layer, adjacent each first spacer.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein the source/drain regions are raised and faceted. 
     
     
         15 . The semiconductor device according to  claim 13 , further comprising a silicide on the source/drain regions. 
     
     
         16 . The semiconductor device according to  claim 12 , wherein the silicon-containing layer comprises silicon germanium having a thickness of about 8 nm to about 12 nm. 
     
     
         17 . The semiconductor device according to  claim 12 , wherein the silicon-containing layer comprises carbon doped silicon (Si:C). 
     
     
         18 . A semiconductor device comprising:
 a silicon substrate;   a buried oxide (BOX) layer on the silicon substrate;   a silicon layer having a thickness of about 6 nm to about 8 nm on the BOX layer;   a high-k metal gate electrode formed on the silicon layer;   an epitaxially formed silicon germanium layer on the silicon layer, surrounding at least a bottom portion of the high-k metal gate electrode;   a first spacer on the silicon germanium layer on each side of the high-k metal gate electrode;   a second spacer on each first spacer; and   a raised faceted source/drain region on the silicon germanium layer, adjacent each first spacer.   
     
     
         19 . The semiconductor device according to  claim 18 , further comprising a silicide on the source/drain regions. 
     
     
         20 . The semiconductor device according to  claim 18 , wherein the silicon germanium has a thickness of about 8 nm to about 12 nm.

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