Etsoi with reduced extension resistance

Abstract

A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, the method comprising:
 forming an SOI substrate;   epitaxially forming a silicon-containing layer on the SOI substrate; and   forming a gate electrode on the epitaxially formed silicon-containing layer.   
     
     
         2 . The method according to  claim 1 , wherein the SOI substrate comprises a thin silicon layer on a silicon substrate with a buried oxide layer (BOX) in between, the thin silicon layer having a thickness of about 6 nm to about 8 nm. 
     
     
         3 . The method according to  claim 1 , further comprising:
 removing the gate electrode; and   forming a replacement gate electrode.   
     
     
         4 . The method according to  claim 1 , further comprising:
 forming a first spacer on each side of the gate electrode.   
     
     
         5 . The method according to  claim 4 , further comprising:
 forming raised source/drain regions adjacent each first spacer.   
     
     
         6 . The method according to  claim 5 , comprising forming the source/drain regions as faceted source/drain regions. 
     
     
         7 . The method according to  claim 5 , further comprising:
 forming a second spacer on each first spacer; and   forming a silicide on the source/drain regions.   
     
     
         8 . The method according to  claim 7 , further comprising:
 removing the gate electrode, thereby exposing a portion of the silicon-containing layer; and   removing the exposed portion of the silicon-containing layer.   
     
     
         9 . The method according to  claim 8 , wherein removing the exposed portion of the silicon-containing layer comprises:
 selectively etching the silicon-containing layer; and   stopping on the SOI substrate.   
     
     
         10 . The method according to  claim 8 , further comprising forming a replacement gate electrode on the SOI substrate between the first spacers. 
     
     
         11 . The method according to  claim 10 , wherein the replacement gate electrode comprises a high-k metal gate electrode. 
     
     
         12 . The method according to  claim 1 , comprising forming the silicon-containing layer by epitaxially growing silicon germanium to a thickness of about 8 nm to about 12 nm. 
     
     
         13 . A semiconductor device comprising:
 an SOI substrate;   a gate electrode formed on the SOI substrate;   an epitaxially formed silicon-containing layer on the SOI substrate, surrounding the gate electrode.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein the SOI substrate comprises a thin silicon layer on a silicon substrate with a buried oxide layer (BOX) in between, the thin silicon layer having a thickness of about 6 nm to about 8 nm. 
     
     
         15 . The semiconductor device according to  claim 13 , further comprising:
 a first spacer on the silicon-containing layer on each side of the gate electrode; and   a source/drain region on the silicon-containing layer, adjacent each first spacer.   
     
     
         16 . The semiconductor device according to  claim 15 , wherein the source/drain regions are raised and faceted. 
     
     
         17 . The semiconductor device according to  claim 15 , further comprising a second spacer on each first spacer. 
     
     
         18 . The semiconductor device according to  claim 13 , wherein the gate electrode comprises a high-k metal gate electrode. 
     
     
         19 . The semiconductor device according to  claim 13 , wherein the silicon-containing layer comprises silicon germanium at a thickness of about 8 nm to about 12 nm. 
     
     
         20 . A method of fabricating a semiconductor, the method comprising:
 forming an ETSOI substrate;   epitaxially growing silicon germanium on the ETSOI substrate to a thickness of about 8 nm to about 12 nm;   forming a gate electrode on the epitaxially formed silicon-containing layer;   forming a first spacer on each side of the gate electrode;   epitaxially forming a raised and faceted source/drain region on the silicon-containing layer, adjacent each first spacer;   removing the gate electrode, thereby exposing a portion of the silicon-containing layer;   selectively etching exposed portion of the silicon-containing layer, stopping on the ETSOI substrate;   forming a high-k metal gate electrode on the ETSOI substrate between the first spacers.