Metal gate fill by optimizing etch in sacrificial gate profile

Abstract

A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

1 . A method of fabricating a semiconductor device, the method comprising:
 forming a replaceable gate electrode having a top surface and a bottom surface, the top surface being larger than the bottom surface;   removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening; and   filling the cavity with metal.   
     
     
         2 . The method according to  claim 1 , comprising forming the replaceable gate electrode by:
 forming a layer of amorphous silicon on a substrate, the layer of amorphous silicon having a top surface and a bottom surface; and   etching the amorphous silicon layer such that the top surface is larger than the bottom surface.   
     
     
         3 . The method according to  claim 2 , comprising:
 etching the top portion of the amorphous silicon at a first temperature; and   etching the bottom portion of the amorphous silicon at a second temperature greater than the first.   
     
     
         4 . The method according to  claim 3 , wherein the depth of the top portion comprises about one half a thickness of the amorphous silicon layer. 
     
     
         5 . The method according to  claim 3 , wherein:
 the first temperature is about room temperature; and   the second temperature is about 350° C. to about 400° C.   
     
     
         6 . The method according to  claim 3 , comprising etching the amorphous silicon by reactive ion etching. 
     
     
         7 . The method according to  claim 3 , further comprising forming an oxide sidewall on the etched top portion prior to etching the bottom portion. 
     
     
         8 . The method according to  claim 2 , further comprising implanting Boron (B) dopant increasing in concentration from a first concentration, at the bottom surface, to a second concentration, greater than the first, at the top surface. 
     
     
         9 . The method according to  claim 8 , wherein the second concentration is about four orders of magnitude greater than the first concentration. 
     
     
         10 . The method according to  claim 9 , further comprising applying different energies for doping the top and bottom portions. 
     
     
         11 . The method according to  claim 2 , the method further comprising in-situ doping the amorphous silicon layer with a dopant to form a concentration gradient of the dopant between the top surface and the bottom surface. 
     
     
         12 . The method according to  claim 11 , wherein the dopant comprises B, and the concentration near the top surface is greater than the concentration near the bottom surface. 
     
     
         13 . The method according to  claim 11 , wherein the dopant comprises phosphorus (P), and the concentration near the top surface is less than the concentration near the bottom surface. 
     
     
         14 . A semiconductor device comprising:
 a silicon substrate; and   a metal gate electrode formed on the silicon substrate, the metal gate electrode having a top surface, a bottom surface smaller than the top surface, and side surfaces.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the side surfaces of the metal gate electrode form an angle of about 80° to about 85° with the top surface. 
     
     
         16 . The semiconductor device according to  claim 14 , further comprising sidewall spacers on side surfaces of the metal gate electrode, wherein the metal gate electrode comprises a replacement gate electrode formed by depositing titanium nitride (TiN) or aluminum (Al) between the sidewall spacers. 
     
     
         17 . A method of fabricating a semiconductor, the method comprising:
 forming a layer of amorphous silicon on a substrate, the amorphous silicon layer having a top portion and a bottom portion, and side surfaces;   differentially etching the top portion and the bottom portion to form a replaceable gate electrode having a top surface larger than a bottom surface;   forming sidewall spacers on the side surfaces of the amorphous silicon layer;   removing the amorphous silicon, forming a cavity between the sidewall spacers having a top opening larger than a bottom opening; and   filling the cavity with metal to form a high-k metal gate electrode.   
     
     
         18 . The method according to  claim 17 , comprising:
 etching the top portion at about room temperature;   forming a protective oxide sidewall at a thickness of about 1 nm to about 3 nm on the etched top portion; and   etching the second portion at about 350° C. to about 400° C.   
     
     
         19 . The method according to  claim 17 , comprising implanting a B dopant in the amorphous silicon, prior to etching, such that the top portion comprises a higher concentration of B than the bottom portion. 
     
     
         20 . The method according to  claim 17 , comprising doping the amorphous silicon in situ with a dopant, such that the dopant exhibits a concentration gradient between the top and bottom surfaces of the amorphous silicon layer.