Inventor · disambiguated record
Berthold Reimer
Also filed as: REIMER BERTHOLD
15 granted patents·4 pending applications·75 citations·filing 2010–2018
91Inventor score
Top patents by PatentIndex Score
19 records- 0191US8445344B2Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterningCARTER RICHARD·Filed 2010·Granted May 21, 2013·17 cites·21 claims
- 0290US8247281B2Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayersHEMPEL KLAUS·Filed 2010·Granted Aug 21, 2012·13 cites·18 claims
- 0386US10559593B1Field-effect transistors with a grown silicon-germanium channelGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 11, 2020·11 cites·20 claims
- 0482US8283232B2Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processingBEYER SVEN·Filed 2010·Granted Oct 9, 2012·7 cites·25 claims
- 0576US8815674B1Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regionsGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 26, 2014·5 cites·13 claims
- 0675US8580133B2Methods of controlling the etching of silicon nitride relative to silicon dioxideREIMER BERTHOLD·Filed 2011·Granted Nov 12, 2013·7 cites·18 claims
- 0773US9842762B1Method of manufacturing a semiconductor wafer having an SOI configurationGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 12, 2017·2 cites·20 claims
- 0872US8524591B2Maintaining integrity of a high-K gate stack by passivation using an oxygen plasmaBEYER SVEN·Filed 2010·Granted Sep 3, 2013·3 cites·22 claims
- 0971US8951901B2Superior integrity of a high-K gate stack by forming a controlled undercut on the basis of a wet chemistryBEYER SVEN·Filed 2011·Granted Feb 10, 2015·2 cites·18 claims
- 1070US9054041B2Methods for etching dielectric materials in the fabrication of integrated circuitsGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 9, 2015·2 cites·5 claims
- 1167US8048748B2Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2010·Granted Nov 1, 2011·2 cites·20 claims
- 1264US8703620B2Methods for PFET fabrication using APM solutionsWASYLUK JOANNA·Filed 2012·Granted Apr 22, 2014·2 cites·10 claims
- 1359US8658543B2Methods for pFET fabrication using APM solutionsWASYLUK JOANNA·Filed 2012·Granted Feb 25, 2014·2 cites·7 claims
- 1454US2015137270A1Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistryGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 1549US8357575B2Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayersGLOBALFOUNDRIES INC·Filed 2012·Granted Jan 22, 2013·0 cites·12 claims
- 1644US8716136B1Method of forming a semiconductor structure including a wet etch process for removing silicon nitrideGLOBALFOUNDRIES INC·Filed 2012·Granted May 6, 2014·0 cites·19 claims
- 1743US2015235906A1Methods for etching dielectric materials in the fabrication of integrated circuitsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 1836US2013299874A1Tmah recess for silicon germanium in positive channel region for cmos deviceWASYLUK JOANNA·Filed 2012·Application pending·0 cites
- 1932US2013126984A1Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface LayerREIMER BERTHOLD·Filed 2011·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →