Inventor · disambiguated record
Bharat Krishnan
Also filed as: KRISHNAN BHARAT · KRISHNAN BHARAT V
19 granted patents·13 pending applications·51 citations·filing 2012–2022
91Inventor score
Top patents by PatentIndex Score
32 records- 0192US10062692B1Field effect transistors with reduced parasitic resistances and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 28, 2018·18 cites·18 claims
- 0292US9640423B2Integrated circuits and methods for their fabricationGLOBALFOUNDRIES INC·Filed 2015·Granted May 2, 2017·9 cites·18 claims
- 0389US10811411B1Fin-type field effect transistor with reduced fin bulge and methodGLOBALFOUNDRIES INC·Filed 2019·Granted Oct 20, 2020·4 cites·20 claims
- 0488US10211045B1Microwave annealing of flowable oxides with trap layersGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 19, 2019·5 cites·20 claims
- 0586US10312150B1Protected trench isolation for fin-type field-effect transistorsGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 4, 2019·5 cites·20 claims
- 0680US9287180B2Integrated circuits having finFETs with improved doped channel regions and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 15, 2016·3 cites·20 claims
- 0775US9882052B2Forming defect-free relaxed SiGe finsGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 30, 2018·2 cites·15 claims
- 0868US10134876B2FinFETs with strained channels and reduced on state resistanceGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 20, 2018·1 cites·15 claims
- 0966US9165767B2Semiconductor structure with increased space and volume between shaped epitaxial structuresGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 20, 2015·1 cites·14 claims
- 1064US9559166B2Fabricating transistors having resurfaced source/drain regions with stressed portionsGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 31, 2017·1 cites·19 claims
- 1163US9059218B2Reducing gate expansion after source and drain implant in gate last processGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 16, 2015·1 cites·6 claims
- 1261US11264382B2Fin-type field effect transistor with reduced fin bulge and methodGLOBALFOUNDRIES US INC·Filed 2020·Granted Mar 1, 2022·0 cites·20 claims
- 1361US8912085B1Method and apparatus for adjusting threshold voltage in a replacement metal gate integrationGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 16, 2014·1 cites·17 claims
- 1451US2023260788A1Carbon-nitride-carbon hardmask layerINTEL CORP·Filed 2022·Application pending·0 cites
- 1551US2023422639A1Semiconductor structure including barrier layer between electrode layer and underlying substrateINTEL CORP·Filed 2022·Application pending·0 cites
- 1650US9093476B2Integrated circuits having FinFETs with improved doped channel regions and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 28, 2015·0 cites·20 claims
- 1750US2018130656A1FORMING DEFECT-FREE RELAXED SiGe FINSGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 1849US11094598B2Multiple threshold voltage devicesGLOBALFOUNDRIES US INC·Filed 2019·Granted Aug 17, 2021·0 cites·19 claims
- 1949US10121706B2Semiconductor structure including two-dimensional and three-dimensional bonding materialsGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 6, 2018·0 cites·9 claims
- 2048US10886178B2Device with highly active acceptor doping and method of production thereofGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 2147US9472465B2Methods of fabricating integrated circuitsGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 18, 2016·0 cites·14 claims
- 2246US2016005657A1Semiconductor structure with increased space and volume between shaped epitaxial structuresGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 2343US2015287824A1Integrated circuits with stressed semiconductor substrates and processes for preparing integrated circuits including the stressed semiconductor substratesGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2442US2015214369A1Methods of forming epitaxial semiconductor material on source/drain regions of a finfet semiconductor device and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2540US2015097197A1Finfet with sigma cavity with multiple epitaxial material regionsGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 2639US10056458B2Siloxane and organic-based MOL contact patterningGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 21, 2018·0 cites·19 claims
- 2739US2020312775A1Semiconductor device having a barrier layer made of two dimensional materialsGLOBALFOUNDRIES INC·Filed 2019·Application pending·0 cites
- 2839US2015214345A1Dopant diffusion barrier to form isolated source/drains in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2939US2015194307A1Strained fin structures and methods of fabricationGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 3038US2014070358A1Method of tailoring silicon trench profile for super steep retrograde well field effect transistorQI YI·Filed 2012·Application pending·0 cites
- 3136US2018138177A1Formation of band-edge contactsGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 3235US2017033181A1Methods of forming replacement fins comprised of multiple layers of different semiconductor materialsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →