Inventor · disambiguated record
Arvind Chandrasekaran
Also filed as: CHANDRASEKARAN ARVIND
22 granted patents·11 pending applications·553 citations·filing 2008–2014
95Inventor score
Files withCHANDRASEKARAN ARVIND15QUALCOMM INC14HENDERSON BRIAN MATTHEW1PACKIRISAMY MUTHUKUMARAN1PMC SIERRA US INC1
Top patents by PatentIndex Score
33 records- 0198US8525342B2Dual-side interconnected CMOS for stacked integrated circuitsCHANDRASEKARAN ARVIND·Filed 2010·Granted Sep 3, 2013·248 cites·15 claims
- 0298US7969009B2Through silicon via bridge interconnectQUALCOMM INC·Filed 2008·Granted Jun 28, 2011·175 cites·18 claims
- 0396US9021440B1System and method for automated test script generationPMC SIERRA US INC·Filed 2014·Granted Apr 28, 2015·42 cites·18 claims
- 0490US8354300B2Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuitsQUALCOMM INC·Filed 2010·Granted Jan 15, 2013·13 cites·28 claims
- 0586US8557680B2Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafersCHANDRASEKARAN ARVIND·Filed 2012·Granted Oct 15, 2013·7 cites·20 claims
- 0686US8242543B2Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafersCHANDRASEKARAN ARVIND·Filed 2009·Granted Aug 14, 2012·12 cites·9 claims
- 0781US8451581B2Passive coupler between package substrate and system boardCHANDRASEKARAN ARVIND·Filed 2010·Granted May 28, 2013·6 cites·18 claims
- 0881US8310061B2Stacked die parallel plate capacitorCHANDRASEKARAN ARVIND·Filed 2008·Granted Nov 13, 2012·10 cites·25 claims
- 0979US8076762B2Variable feature interface that induces a balanced stress to prevent thin die warpageCHANDRASEKARAN ARVIND·Filed 2009·Granted Dec 13, 2011·8 cites·20 claims
- 1078US8283776B2Microfabricated pillar fins for thermal managementCHANDRASEKARAN ARVIND·Filed 2010·Granted Oct 9, 2012·4 cites·20 claims
- 1175US9252128B2Panelized backside processing for thin semiconductorsCHANDRASEKARAN ARVIND·Filed 2011·Granted Feb 2, 2016·3 cites·17 claims
- 1275US7900519B2Microfluidic measuring tool to measure through-silicon via depthQUALCOMM INC·Filed 2009·Granted Mar 8, 2011·4 cites·16 claims
- 1373US8513089B2Discontinuous thin semiconductor wafer surface featuresQUALCOMM INC·Filed 2012·Granted Aug 20, 2013·2 cites·18 claims
- 1473US8445994B2Discontinuous thin semiconductor wafer surface featuresCHANDRASEKARAN ARVIND·Filed 2009·Granted May 21, 2013·3 cites·17 claims
- 1572US8883080B2Nano-enhanced evanescence integrated technique (NEET) based microphotonic device and sample analysis systemPACKIRISAMY MUTHUKUMARAN·Filed 2010·Granted Nov 11, 2014·3 cites·20 claims
- 1671US8294280B2Panelized backside processing for thin semiconductorsCHANDRASEKARAN ARVIND·Filed 2009·Granted Oct 23, 2012·4 cites·7 claims
- 1770US8391018B2Semiconductor die-based packaging interconnectCHANDRASEKARAN ARVIND·Filed 2009·Granted Mar 5, 2013·4 cites·16 claims
- 1864US8912043B2Dual-side interconnected CMOS for stacked integrated circuitsQUALCOMM INC·Filed 2013·Granted Dec 16, 2014·1 cites·20 claims
- 1961US8803305B2Hybrid package construction with wire bond and through silicon viasRADOJCIC RATIBOR·Filed 2009·Granted Aug 12, 2014·3 cites·20 claims
- 2052US8877563B2Microfabricated pillar fins for thermal managementCHANDRASEKARAN ARVIND·Filed 2012·Granted Nov 4, 2014·0 cites·18 claims
- 2150US8618539B2Interconnect sensor for detecting delaminationHENDERSON BRIAN MATTHEW·Filed 2009·Granted Dec 31, 2013·1 cites·18 claims
- 2249US8482125B2Conductive sidewall for microbumpsCHANDRASEKARAN ARVIND·Filed 2010·Granted Jul 9, 2013·0 cites·6 claims
- 2349US2013105559A1Conductive sidewall for microbumpsQUALCOMM INC·Filed 2012·Application pending·0 cites
- 2448US2010200957A1Scribe-Line Through Silicon ViasQUALCOMM INC·Filed 2009·Application pending·0 cites
- 2547US2010314725A1Stress Balance Layer on Semiconductor Wafer BacksideQUALCOMM INC·Filed 2009·Application pending·0 cites
- 2647US2010127937A1Antenna Integrated in a Semiconductor ChipQUALCOMM INC·Filed 2008·Application pending·0 cites
- 2746US2011215472A1Through Silicon via Bridge InterconnectQUALCOMM INC·Filed 2011·Application pending·0 cites
- 2838US2012012991A1Integrated shielding for a package-on-package systemCHANDRASEKARAN ARVIND·Filed 2010·Application pending·0 cites
- 2937US2011012239A1Barrier Layer On Polymer Passivation For Integrated Circuit PackagingQUALCOMM INC·Filed 2010·Application pending·0 cites
- 3037US2011193211A1Surface Preparation of Die for Improved Bonding StrengthQUALCOMM INC·Filed 2010·Application pending·0 cites
- 3137US2012025362A1Reinforced Wafer-Level Molding to Reduce WarpageCHANDRASEKARAN ARVIND·Filed 2010·Application pending·0 cites
- 3236US2011193212A1Systems and Methods Providing Arrangements of ViasQUALCOMM INC·Filed 2010·Application pending·0 cites
- 3328US2011221053A1Pre-processing to reduce wafer level warpageQUALCOMM INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →