Inventor · disambiguated record
Chuen-Jye Lin
Also filed as: LIN CHUEN-JYE
16 granted patents·6 pending applications·552 citations·filing 1999–2010
95Inventor score
Top patents by PatentIndex Score
22 records- 0199US7902679B2Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bumpMEGICA CORP·Filed 2007·Granted Mar 8, 2011·111 cites·20 claims
- 0297US6917119B2Low fabrication cost, high performance, high reliability chip scale packageMEGIC CORP·Filed 2003·Granted Jul 12, 2005·106 cites·10 claims
- 0397US6642136B1Method of making a low fabrication cost, high performance, high reliability chip scale packageMEGIC CORP·Filed 2001·Granted Nov 4, 2003·123 cites·36 claims
- 0493US7355288B2Low fabrication cost, high performance, high reliability chip scale packageMEGICA CORP·Filed 2005·Granted Apr 8, 2008·20 cites·26 claims
- 0593US7338890B2Low fabrication cost, high performance, high reliability chip scale packageMEGICA CORP·Filed 2005·Granted Mar 4, 2008·23 cites·25 claims
- 0693US6815324B2Reliable metal bumps on top of I/O pads after removal of test probe marksMEGIC CORP·Filed 2001·Granted Nov 9, 2004·70 cites·28 claims
- 0790US8158508B2Structure and manufacturing method of a chip scale packageLIN MOU-SHIUNG·Filed 2007·Granted Apr 17, 2012·13 cites·36 claims
- 0883US9369175B2Low fabrication cost, high performance, high reliability chip scale packageLEE JIN-YUAN·Filed 2007·Granted Jun 14, 2016·9 cites·24 claims
- 0981US7465653B2Reliable metal bumps on top of I/O pads after removal of test probe marksMEGICA CORP·Filed 2004·Granted Dec 16, 2008·22 cites·19 claims
- 1078US8481418B2Low fabrication cost, high performance, high reliability chip scale packageLEE JIN-YUAN·Filed 2007·Granted Jul 9, 2013·6 cites·42 claims
- 1178US7105920B2Substrate design to improve chip package reliabilityTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Sep 12, 2006·23 cites·18 claims
- 1272US8178967B2Low fabrication cost, high performance, high reliability chip scale packageLEE JIN-YUAN·Filed 2007·Granted May 15, 2012·3 cites·23 claims
- 1368US8901733B2Reliable metal bumps on top of I/O pads after removal of test probe marksHUANG CHING-CHENG·Filed 2008·Granted Dec 2, 2014·4 cites·22 claims
- 1467US7638887B2Package structure and fabrication method thereofTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Dec 29, 2009·3 cites·8 claims
- 1556US2009267213A1Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bumpMEGICA CORP·Filed 2009·Application pending·0 cites
- 1651US2011024905A1Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bumpMEGICA CORP·Filed 2010·Application pending·0 cites
- 1751US2011024902A1Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bumpMEGICA CORP·Filed 2010·Application pending·0 cites
- 1849US8685834B2Fabrication method of package structure with simplified encapsulation structure and simplified wiringTSAO PEI-HAW·Filed 2009·Granted Apr 1, 2014·0 cites·10 claims
- 1949US6075281AModified lead finger for wire bondingVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Jun 13, 2000·16 cites·14 claims
- 2042US2006163729A1Structure and manufacturing method of a chip scale packageLIN MOU-SHIUNG·Filed 2006·Application pending·0 cites
- 2139US2006060980A1Ic package having ground ic chip and method of manufacturing sameTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 2235US2003099907A1Process of rectifying a wafer thicknessFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →