Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump

Abstract

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

1 . A chip package comprising:
 a substrate;   a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;   a copper pillar between said first contact point and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers, and wherein said copper pillar is connected to said first contact point through said opening;   a second metal layer between said first contact point and said copper pillar, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said copper pillar is connected to said first contact point through said second metal layer;   a solder between said copper pillar and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said copper pillar; and   an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar.   
     
     
         2 . The chip package of  claim 1  further comprising a nickel-containing layer between said solder and said copper pillar. 
     
     
         3 . The chip package of  claim 2 , wherein said nickel-containing layer has a thickness between 1 and 10 micrometers. 
     
     
         4 . The chip package of  claim 1 , wherein said second metal layer comprises titanium. 
     
     
         5 . The chip package of  claim 1 , wherein said metal pad comprises copper. 
     
     
         6 . The chip package of  claim 1 , wherein said substrate comprises a solder mask, a second contact point in a channel in said solder mask, a third contact point in said channel, wherein said second contact point is separate from said third contact point, and wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, a first interconnect covered by said solder mask and connected to said second contact point through said first sidewall, and a second interconnect covered by said solder mask and connected to said third contact point through said second sidewall, wherein said solder is joined with said second contact point. 
     
     
         7 . A chip package comprising:
 a substrate;   a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;   a copper-containing layer between said first contact point and said substrate, wherein said copper-containing layer is connected to said first contact point through said opening;   a second metal layer between said first contact point and said copper-containing layer, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said copper-containing layer is connected to said first contact point through said second metal layer;   a solder between said copper-containing layer and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said copper-containing layer; and   an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said solder.   
     
     
         8 . The chip package of  claim 7 , wherein said second metal layer comprises titanium. 
     
     
         9 . The chip package of  claim 7 , wherein said metal pad comprises copper. 
     
     
         10 . The chip package of  claim 7 , wherein said copper-containing layer has a thickness between 10 and 100 micrometers. 
     
     
         11 . The chip package of  claim 7 , wherein said substrate comprises a solder mask, a second contact point in a channel in said solder mask, a third contact point in said channel, wherein said second contact point is separate from said third contact point, and wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, a first interconnect covered by said solder mask and connected to said second contact point through said first sidewall, and a second interconnect covered by said solder mask and connected to said third contact point through said second sidewall, wherein said solder is joined with said second contact point. 
     
     
         12 . A chip package comprising:
 a substrate;   a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;   a copper-containing layer between said first contact point and said substrate, wherein said copper-containing layer is connected to said first contact point through said opening;   a second metal layer between said first contact point and said copper-containing layer, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said copper-containing layer is connected to said first contact point through said second metal layer;   a solder between said copper-containing layer and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said copper-containing layer;   a nickel-containing layer between said copper-containing layer and said solder; and   an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said solder.   
     
     
         13 . The chip package of  claim 12 , wherein said second metal layer comprises titanium. 
     
     
         14 . The chip package of  claim 12 , wherein said metal pad comprises copper. 
     
     
         15 . The chip package of  claim 12 , wherein said copper-containing layer has a thickness between 10 and 100 micrometers. 
     
     
         16 . The chip package of  claim 12 , wherein said nickel-containing layer has a thickness between 1 and 10 micrometers. 
     
     
         17 . A chip package comprising:
 a substrate;   a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;   a nickel-containing layer between said first contact point and said substrate, wherein said nickel-containing layer is connected to said first contact point through said opening;   a second metal layer between said first contact point and said nickel-containing layer, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said nickel-containing layer is connected to said first contact point through said second metal layer;   a solder between said nickel-containing layer and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said nickel-containing layer; and   an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said solder.   
     
     
         18 . The chip package of  claim 17 , wherein said second metal layer comprises titanium. 
     
     
         19 . The chip package of  claim 17 , wherein said metal pad comprises copper. 
     
     
         20 . The chip package of  claim 17 , wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.