Inventor · disambiguated record
Tzu-Kun Ku
Also filed as: KU TZU-KUN
21 granted patents·14 pending applications·207 citations·filing 1995–2018
94Inventor score
Files withIND TECH RES INST13CENTRILLION TECH TAIWAN CO LTD3SILICON INTEGRATED SYS CORP3CHEN JUI-CHIN2HSU TZU-CHIEN2
Top patents by PatentIndex Score
35 records- 0191US5856237AInsitu formation of TiSi2/TiN bi-layer structures using self-aligned nitridation treatment on underlying CVD-TiSi2 layerIND TECH RES INST·Filed 1997·Granted Jan 5, 1999·82 cites·7 claims
- 0283US10416114B2Structures and manufacture method of electrochemical unitsIND TECH RES INST·Filed 2016·Granted Sep 17, 2019·3 cites·37 claims
- 0379US8445995B2Semiconductor structure with conductive plug in an oxide layerLIN CHA-HSIN·Filed 2011·Granted May 21, 2013·5 cites·5 claims
- 0472US8309402B2Method of fabricating oxide material layer with openings attached to device layersLIN CHA-HSIN·Filed 2011·Granted Nov 13, 2012·3 cites·21 claims
- 0571US9368475B2Semiconductor device and manufacturing method thereofIND TECH RES INST·Filed 2015·Granted Jun 14, 2016·2 cites·9 claims
- 0671US6071552AInsitu formation of TiSi2 /TiN bi-layer structures using self-aligned nitridation treatment on underlying CVD-TiSi2 layerIND TECH RES INST·Filed 1998·Granted Jun 6, 2000·25 cites·12 claims
- 0771US5643032AMethod of fabricating a field emission deviceNAT SCIENCE COUNCIL·Filed 1995·Granted Jul 1, 1997·24 cites·15 claims
- 0867US6184135B1Insitu formation of TiSi2/TiN bi-layer structures using self-aligned nitridation treatment on underlying CVD-TiSi2 layerIND TECH RES INST·Filed 1998·Granted Feb 6, 2001·20 cites·9 claims
- 0966US9257322B2Method for manufacturing through substrate via (TSV), structure and control method of TSV capacitanceCHEN ERH-HAO·Filed 2012·Granted Feb 9, 2016·3 cites·16 claims
- 1066US9093312B2Semiconductor device and manufacturing method thereofIND TECH RES INST·Filed 2013·Granted Jul 28, 2015·2 cites·9 claims
- 1154US6713379B1Method for forming a damascene structureSILICON INTEGRATED SYS CORP·Filed 2003·Granted Mar 30, 2004·6 cites·19 claims
- 1252US10913070B2Microarray carrier assemblyCENTRILLION TECH TAIWAN CO LTD·Filed 2018·Granted Feb 9, 2021·0 cites·20 claims
- 1352US9257338B2TSV substrate structure and the stacked assembly thereofIND TECH RES INST·Filed 2015·Granted Feb 9, 2016·0 cites·3 claims
- 1452US2013214390A1Tsv substrate structure and the stacked assembly thereofIND TECH RES INST·Filed 2013·Application pending·0 cites
- 1549US6784075B2Method of forming shallow trench isolation with silicon oxynitride barrier filmSILICON INTEGRATED SYS CORP·Filed 2002·Granted Aug 31, 2004·5 cites·10 claims
- 1648US10732166B2Method for in-line measurement of quality of microarrayCENTRILLION TECH TAIWAN CO LTD·Filed 2018·Granted Aug 4, 2020·0 cites·18 claims
- 1748US6720235B2Method of forming shallow trench isolation in a semiconductor substrateSILICON INTEGRATED SYSTEM CORP·Filed 2002·Granted Apr 13, 2004·5 cites·16 claims
- 1848US2012322249A1Manufacturing method of semiconductor structureCHEN JUI-CHIN·Filed 2012·Application pending·0 cites
- 1947US2012133030A1Tsv substrate structure and the stacked assembly thereofWANG CHUNG-CHIH·Filed 2010·Application pending·0 cites
- 2045US10872924B2Microarray and method for forming the sameCENTRILLION TECH TAIWAN CO LTD·Filed 2018·Granted Dec 22, 2020·0 cites·14 claims
- 2145US2012119375A1Semiconductor structure and manufacturing method thereofCHEN JUI-CHIN·Filed 2010·Application pending·0 cites
- 2243US6184130B1Silicide glue layer for W-CVD plug applicationIND TECH RES INST·Filed 1997·Granted Feb 6, 2001·9 cites·23 claims
- 2343US2014238725A1Method of flattening surface of conductive structure and conductive structure with flattened surfaceTECHNOLOGY RES INST IND·Filed 2013·Application pending·0 cites
- 2441US2014175614A1Wafer stacking structure and method of manufacturing the sameIND TECH RES INST·Filed 2012·Application pending·0 cites
- 2541US2014175655A1Chip bonding structure and manufacturing method thereofIND TECH RES INST·Filed 2013·Application pending·0 cites
- 2640US6258716B1CVD titanium silicide for contact hole plugsIND TECH RES INST·Filed 1999·Granted Jul 10, 2001·8 cites·8 claims
- 2739US6743690B2Method of forming a metal-oxide semiconductor transistorSILICON INTEGRATED SYS CORP·Filed 2002·Granted Jun 1, 2004·1 cites·10 claims
- 2838US2001000158A1Silicide glue layer for W-CVD plug applicationFiled 2000·Application pending·0 cites
- 2937US2014008652A1Through-substrate via structureHSU TZU-CHIEN·Filed 2012·Application pending·0 cites
- 3037US2013270713A1Dual damascene structure having through silicon via and manufacturing method thereofLIAO SUE-CHEN·Filed 2012·Application pending·0 cites
- 3136US2003116826A1Interconnect structure capped with a metallic barrier layer and method fabrication thereofFiled 2001·Application pending·0 cites
- 3235US2002182850A1Interconnect structure manufacturing processFiled 2001·Application pending·0 cites
- 3335US2012127625A1Trench capacitor structures and method of manufacturing the sameWANG CHUNG-CHIH·Filed 2010·Application pending·0 cites
- 3435US2013161825A1Through substrate via structure and method for fabricating the sameHSU TZU-CHIEN·Filed 2011·Application pending·0 cites
- 3534US5930671ACVD titanium silicide for contract hole plugsIND TECH RES INST·Filed 1997·Granted Jul 27, 1999·4 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →