Silicide glue layer for W-CVD plug application

Abstract

A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

What is claimed is:  
     
         1 . A method of forming tungsten plug metallization in the fabrication of integrated circuits comprising: 
 providing semiconductor device structures in and on a semiconductor substrate;    providing an insulating layer covering said semiconductor device structures wherein a contact opening is made through said insulating layer to one of said semiconductor device structures;    depositing a silicide layer conformally over the surface of said insulating layer and within said contact opening wherein said silicide layer acts as an ohmic contact and glue layer;    depositing a tungsten layer overlying said silicide layer; and    removing said tungsten layer and said silicide layer not within said contact opening to complete said formation of said tungsten plug metallization in said fabrication of said integrated circuit.    
     
     
         2 . The method according to    claim 1    wherein said semiconductor device structures include source and drain regions and polysilicon gate electrodes and interconnection lines.  
     
     
         3 . The method according to    claim 1    wherein said semiconductor device structures include source and drain regions and polysilicon gate electrodes and interconnection lines and first level metal lines.  
     
     
         4 . The method according to    claim 1    wherein said silicide layer is deposited by chemical vapor deposition has a thickness of between about 200 and 500 Angstroms.  
     
     
         5 . The method according to    claim 1    wherein said silicide layer is deposited by physical vapor deposition has a thickness of between about 200 and 500 Angstroms.  
     
     
         6 . The method according to    claim 1    wherein said tungsten layer is deposited using WF 6  gas and SiH 4  as precursors.  
     
     
         7 . The method according to    claim 1    wherein said tungsten layer is deposited using WF 6  gas and SiH 2 Cl 2  as precursors.  
     
     
         8 . The method according to    claim 1    wherein said tungsten layer is deposited using WF 6  gas and H 2  as precursors.  
     
     
         9 . The method according to    claim 1    wherein said removing said tungsten layer not within said contact opening is performed by reactive ion etching.  
     
     
         10 . The method according to    claim 1    wherein said removing said tungsten layer not within said contact opening is performed by chemical mechanical polishing.  
     
     
         11 . A method of forming tungsten plug metallization in the fabrication of integrated circuits comprising: 
 providing semiconductor device structures in and on a semiconductor substrate;    providing an insulating layer covering said semiconductor device structures wherein a contact opening is made through said insulating layer to one of said semiconductor device structures;    depositing a silicide layer conformally over the surface of said insulating layer and within said contact opening wherein said silicide layer acts as an ohmic contact and glue layer;    selectively removing said silicide layer not within said contact opening; and    selectively depositing a tungsten layer overlying said silicide layer within said contact opening to complete said formation of said tungsten plug metallization in said fabrication of said integrated circuit.    
     
     
         12 . The method according to    claim 11    wherein said semiconductor device structures include source and drain regions and polysilicon gate electrodes and interconnection lines.  
     
     
         13 . The method according to    claim 11    wherein said semiconductor device structures include source and drain regions and polysilicon gate electrodes and interconnection lines and first level metal lines.  
     
     
         14 . The method according to    claim 11    wherein said silicide layer is deposited by chemical vapor deposition has a thickness of between about 200 and 500 Angstroms.  
     
     
         15 . The method according to    claim 11    wherein said silicide layer is deposited by physical vapor deposition has a thickness of between about 200 and 500 Angstroms.  
     
     
         16 . The method according to    claim 11    wherein said selectively removing said silicide layer is done by chemical mechanical polishing.  
     
     
         17 . The method according to    claim 11    wherein said tungsten layer is selectively deposited using WF 6  gas and SiH 4  as precursors.  
     
     
         18 . The method according to    claim 11    wherein said tungsten layer is selectively deposited using WF 6  gas and SiH 2 Cl 2  as precursors.  
     
     
         19 . The method according to    claim 1    wherein said tungsten layer is selectively deposited using WF 6  gas and H 2  as precursors.  
     
     
         20 . An integrated circuit device comprising: 
 semiconductor device structures in and on a semiconductor substrate;    an insulating layer covering said semiconductor device structures;    a patterned metal layer overlying said insulating layer;    a tungsten plug extending through said insulating layer connecting said patterned metal layer with one of said semiconductor device structures; and    a silicide layer lying between said tungsten plug and said insulating layer and between said tungsten plug and said one of said semiconductor device structures wherein said silicide layer acts as an ohmic contact and glue layer.    
     
     
         21 . The device according to    claim 20    wherein said semiconductor device structures include source and drain regions and polysilicon gate electrodes and interconnection lines.  
     
     
         22 . The method according to    claim 20    wherein said semiconductor device structures include source and drain regions and polysilicon gate electrodes and interconnection lines and first level metal lines.  
     
     
         23 . The device according to    claim 20    wherein said silicide layer has a thickness of between about 200 and 500 Angstroms.