Inventor · disambiguated record
David Paul Brunco
Also filed as: BRUNCO DAVID · BRUNCO DAVID P · BRUNCO DAVID PAUL
30 granted patents·5 pending applications·136 citations·filing 2004–2019
95Inventor score
Files withGLOBALFOUNDRIES INC23IMEC6IMEC INTER UNI MICRO ELECTR2BRUNCO DAVID PAUL1GLOBALFOUNDRIES US INC1
Top patents by PatentIndex Score
35 records- 0194US10014409B1Method and structure to provide integrated long channel vertical FinFET deviceGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 3, 2018·10 cites·9 claims
- 0293US8828839B2Methods for fabricating electrically-isolated finFET semiconductor devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 9, 2014·15 cites·20 claims
- 0392US10002793B1Sub-fin doping methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 19, 2018·8 cites·16 claims
- 0489US9006705B2Device with strained layer for quantum well confinement and method for manufacturing thereofIMEC·Filed 2013·Granted Apr 14, 2015·8 cites·15 claims
- 0588US10347541B1Active gate contacts and method of fabrication thereofGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 9, 2019·6 cites·20 claims
- 0688US6869892B1Method of oxidizing work pieces and oxidation systemTOKYO ELECTRON LTD·Filed 2004·Granted Mar 22, 2005·43 cites·9 claims
- 0787US9029217B1Band engineered semiconductor device and method for manufacturing thereofIMEC·Filed 2015·Granted May 12, 2015·5 cites·8 claims
- 0886US9583557B2Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetimeGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 28, 2017·5 cites·14 claims
- 0984US10727067B2Late gate cut using selective conductor depositionGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 28, 2020·3 cites·17 claims
- 1084US9911740B2Method, apparatus, and system having super steep retrograde well with engineered dopant profilesGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 6, 2018·3 cites·13 claims
- 1184US9299809B2Methods of forming fins for a FinFET device wherein the fins have a high germanium contentGLOBALFOUNDRIES INC·Filed 2012·Granted Mar 29, 2016·7 cites·33 claims
- 1281US7517765B2Method for forming germanides and devices obtained thereofIMEC INTER UNI MICRO ELECTR·Filed 2006·Granted Apr 14, 2009·11 cites·19 claims
- 1379US10403742B2Field-effect transistors with fins formed by a damascene-like processGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 3, 2019·2 cites·14 claims
- 1479US9929159B2Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium finsGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 27, 2018·2 cites·11 claims
- 1570US10811422B2Semiconductor recess to epitaxial regions and related integrated circuit structureGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 20, 2020·1 cites·19 claims
- 1666US8963225B2Band engineered semiconductor device and method for manufacturing thereofIMEC·Filed 2013·Granted Feb 24, 2015·1 cites·13 claims
- 1762US8207030B2Method for producing nMOS and pMOS devices in CMOS processingBRUNCO DAVID PAUL·Filed 2009·Granted Jun 26, 2012·4 cites·18 claims
- 1860US8828826B2Method for manufacturing a transistor device comprising a germanium based channel layerIMEC·Filed 2013·Granted Sep 9, 2014·1 cites·14 claims
- 1959US10325913B2Method, apparatus, and system having super steep retrograde well with engineered dopant profilesGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 18, 2019·0 cites·19 claims
- 2058US9953872B2Semiconductor structure with self-aligned wells and multiple channel materialsGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 24, 2018·0 cites·8 claims
- 2158US9257557B2Semiconductor structure with self-aligned wells and multiple channel materialsGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 9, 2016·0 cites·11 claims
- 2257US8354344B2Methods for forming metal-germanide layers and devices obtained therebyIMEC·Filed 2008·Granted Jan 15, 2013·1 cites·25 claims
- 2356US10497703B2Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium finsGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 3, 2019·0 cites·20 claims
- 2456US2019273148A1Field-effect transistors with fins formed by a damascene-like processGLOBALFOUNDRIES INC·Filed 2019·Application pending·0 cites
- 2555US9793168B2Semiconductor structure with self-aligned wells and multiple channel materialsGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 17, 2017·0 cites·8 claims
- 2648US2015146341A1ALD dielectric films with leakage-reducing impurity layersGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 2747US10325811B2Field-effect transistors with fins having independently-dimensioned sectionsGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 18, 2019·0 cites·17 claims
- 2847US9490123B2Methods of forming strained epitaxial semiconductor material(S) above a strain-relaxed buffer layerGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 8, 2016·0 cites·8 claims
- 2944US9064702B2Method for manufacturing semiconductor devicesIMEC·Filed 2013·Granted Jun 23, 2015·0 cites·14 claims
- 3044US2015318169A1Methods of forming epitaxial semiconductor cladding material on fins of a finfet semiconductor deviceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 3142US11081398B2Method and structure to provide integrated long channel vertical FinFet deviceGLOBALFOUNDRIES US INC·Filed 2018·Granted Aug 3, 2021·0 cites·20 claims
- 3242US8211812B2Method for fabricating a high-K dielectric layerRAGNARSSON LARS-AKE·Filed 2008·Granted Jul 3, 2012·0 cites·15 claims
- 3342US2016035727A1Cmos structure with beneficial nmos and pmos band offsetsGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 3440US2008254605A1Method of reducing the interfacial oxide thicknessIMEC INTER UNI MICRO ELECTR·Filed 2007·Application pending·0 cites
- 3538US10062612B2Method and system for constructing FINFET devices having a super steep retrograde wellGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 28, 2018·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →