Cmos structure with beneficial nmos and pmos band offsets

Abstract

A CMOS structure with beneficial nMOS and pMOS band offsets is disclosed. A first silicon germanium layer is formed on a semiconductor substrate. A second silicon germanium layer is formed on the first silicon germanium layer. The second silicon germanium layer has a higher germanium percentage than the first silicon germanium layer. Furthermore, the germanium concentration of the two layers is selected such that there is a beneficial band offset for both N-type field effect transistors and P-type field effect transistors in a CMOS structure.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor substrate;   a first silicon germanium layer disposed on the semiconductor substrate;   a second silicon germanium layer disposed on the first silicon germanium layer; and   
       a plurality of shallow trench isolation regions formed in the second silicon germanium layer and partially into the first silicon germanium layer; wherein the first silicon germanium layer has a first germanium concentration, and wherein the second silicon germanium layer has a second germanium concentration, and wherein the second germanium concentration is greater than the first germanium concentration. 
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first germanium concentration ranges from about 40 percent to about 60 percent, and the second germanium concentration ranges from about 90 percent to about 95 percent. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the first germanium concentration ranges from about 60 percent to about 70 percent, and the second germanium concentration ranges from about 75 percent to about 90 percent. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the first germanium concentration ranges from about 80 percent to about 85 percent, and the second germanium concentration ranges from about 90 percent to about 95 percent. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the first silicon germanium layer has a germanium atomic fraction y and second silicon germanium layer has a germanium atomic fraction x such that 0.8≦x≦1 and y≧−3.5x+3.6. 
     
     
         6 . A semiconductor structure comprising:
 a semiconductor substrate;   a first silicon germanium layer disposed on the semiconductor substrate;   a second silicon germanium layer disposed on the first silicon germanium layer; and   a plurality of shallow trench isolation regions formed in the second silicon germanium layer and partially into the first silicon germanium layer; wherein the first silicon germanium layer has a first germanium concentration, and wherein the second silicon germanium layer has a second germanium concentration, and wherein the second germanium concentration is greater than the first germanium concentration; and   wherein a conduction band offset between the second silicon germanium layer and the first silicon germanium layer ranges from about −0.05 eV to about −0.15 eV, and wherein a valence band offset between the second silicon germanium layer and the first silicon germanium layer ranges from about 0.05 eV to about 0.4 eV.   
     
     
         7 . The semiconductor structure of  claim 6 , further comprising an nMOS region and a pMOS region, and wherein the first silicon germanium layer comprises a p-doped region in the nMOS region of the semiconductor structure and an n-doped region in the pMOS region of the semiconductor structure. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein a source region and a drain region for the pMOS region contains compressively-strained silicon germanium with a germanium concentration higher than that of the second silicon germanium layer. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein a source region and a drain region for the nMOS region contain tensile-strained silicon or silicon germanium with a germanium concentration at least 10% lower than that of the first silicon germanium layer. 
     
     
         10 . The semiconductor structure of  claim 6 , wherein the first silicon germanium layer has a thickness that ranges from about 100 nanometers to about 2000 nanometers. 
     
     
         11 . The semiconductor structure of  claim 6 , wherein the second silicon germanium layer has a thickness that ranges from about 10 nanometers to about 90 nanometers. 
     
     
         12 . The semiconductor structure of  claim 6 , further comprising:
 a p-type field effect transistor formed on the second silicon germanium layer; and   an n-type field effect transistor formed on the second silicon germanium layer and disposed adjacent to the p-type field effect transistor.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein the p-type field effect transistor is a fin-type field effect transistor and wherein the n-type field effect transistor is a fin-type field effect transistor. 
     
     
         14 . A method of forming a semiconductor structure, comprising:
 forming a first silicon germanium layer on a semiconductor substrate, the first silicon germanium layer having a first germanium concentration;   forming a p-doped region in the first silicon germanium layer;   forming an n-doped region in the first silicon germanium layer; and   forming a second silicon germanium layer on the first silicon germanium layer, the second silicon germanium layer having a second germanium concentration that is greater than the first germanium concentration.   
     
     
         15 . The method of  claim 14 , further comprising forming a plurality of shallow trench isolation regions in the second silicon germanium layer and partially into the first silicon germanium layer. 
     
     
         16 . The method of  claim 14 , further comprising forming a plurality of fins in the second silicon germanium layer. 
     
     
         17 . The method of  claim 16 , further comprising forming stressor regions on the plurality of fins. 
     
     
         18 . The method of  claim 17 , wherein forming stressor regions comprises:
 depositing a compressively-strained silicon germanium layer on a subset of the plurality of fins that correspond to a PFET device; and   depositing a tensile-strained silicon germanium layer on a subset of the plurality of fins that correspond to an NFET device.   
     
     
         19 . The method of  claim 18 , further comprising:
 forming a first set of fin recesses in a plurality of nMOS source and drain regions prior to performing a deposition of strained source drain materials; and   forming a second set of fin recesses in a plurality of pMOS source and drain regions prior to performing a deposition of strained source drain materials;   
       wherein the first set of fin recesses is at least 5 nanometers deeper than the second set of fin recesses. 
     
     
         20 . The method of  claim 14 , wherein a conduction band offset between the second silicon germanium layer and the first silicon germanium layer ranges from about −0.05 eV to about −0.15 eV, and wherein a valence band offset between the second silicon germanium layer and first silicon germanium layer ranges from about 0.05 eV to about 0.4 eV.