Field-effect transistors with fins formed by a damascene-like process

Abstract

Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

What is claimed is: 
     
         1 . A structure formed using a substrate, the structure comprising:
 a layer stack on the substrate, the layer stack having a first region including a first dielectric layer and a second dielectric layer arranged over the first dielectric layer, the first dielectric layer comprised of a first material, and the second dielectric layer comprised of a second material with etch selectivity to the first material; and   a first plurality of fins projecting from the substrate through the first dielectric layer and the second dielectric layer.   
     
     
         2 . The structure of  claim 1  wherein each of the first plurality of fins includes an equal-height section arranged above a top surface of the second dielectric layer. 
     
     
         3 . The structure of  claim 1  wherein the layer stack has a second region that further includes a third dielectric layer arranged over the second dielectric layer, and further comprising:
 a second plurality of fins projecting from the substrate through the first dielectric layer, the second dielectric layer, and the third dielectric layer, each of the second plurality of fins including a section arranged above a top surface of the third dielectric layer, 
 wherein the section of each of the first plurality of fins has a first height relative to the top surface of the second dielectric layer, the section of each of the second plurality of fins has a second height relative to the top surface of the third dielectric layer, and the first height is greater than the second height. 
 
     
     
         4 . The structure of  claim 1  wherein the section of each of the first plurality of fins has a plurality of sidewalls that are oriented vertically relative to the top surface of the second dielectric layer. 
     
     
         5 . The structure of  claim 1  wherein the first material is silicon dioxide, and the second material is silicon nitride. 
     
     
         6 . The structure of  claim 1  wherein the layer stack includes a third dielectric layer arranged over the first dielectric layer and a fourth dielectric layer arranged between the third dielectric layer and the first dielectric layer, the first plurality of fins project through the third dielectric layer and the fourth dielectric layer, and the first section of each of the first plurality of fins is arranged above a top surface of the fourth dielectric layer. 
     
     
         7 . The structure of  claim 6  wherein the third dielectric layer is comprised of the first material, and the second dielectric layer is comprised of the second material. 
     
     
         8 . The structure of  claim 7  wherein the first material is silicon dioxide, and the second material is silicon nitride. 
     
     
         9 . The method of  claim 1  wherein the first plurality of fins are comprised of single crystal silicon that has an epitaxial relationship with the substrate. 
     
     
         10 . The method of  claim 1  wherein the first plurality of fins are comprised of a single crystal semiconductor material that has an epitaxial relationship with the substrate. 
     
     
         11 . The structure of  claim 1  wherein each of the first plurality of fins includes a first section comprised of a first semiconductor material and a second section comprised of a second semiconductor material. 
     
     
         12 . The method of  claim 11  wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium. 
     
     
         13 . The method of  claim 11  wherein the first semiconductor material is silicon, and the second semiconductor material is germanium. 
     
     
         14 . The method of  claim 11  wherein the first semiconductor material is silicon, and the second semiconductor material is carbon-doped silicon. 
     
     
         15 . The method of  claim 11  wherein the first section of each of the first plurality of fins is arranged at or below at top surface of the second dielectric layer. 
     
     
         16 . The method of  claim 11  wherein the first semiconductor material and the second semiconductor material have an epitaxial relationship. 
     
     
         17 . The structure of  claim 11  wherein the second section of each of the first plurality of fins is arranged over the first section of each of the first plurality of fins. 
     
     
         18 . The structure of  claim 1  wherein each of the first plurality of fins includes a section arranged above a top surface of the second dielectric layer, and further comprising:
 a gate structure arranged to overlap with the section of each of the first plurality of fins. 
 
     
     
         19 . The structure of  claim 17  wherein the gate structure includes a gate electrode containing one or more work function metal layers.