Integrated circuit package having pin-up interconnect

Abstract

An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

1 .- 13 . (canceled) 
     
     
         14 . An integrated circuit packaging, comprising:
 a plurality of electrical circuits developed using a first patterned conductive layer on the base, wherein an electrical circuit formed by using a masking material;   a stud conductive layer disposed on at least one side of the first patterned conductive layer developed by a second layer photo-resist material on the masking material;   an epoxy or polyimide compound developed on the base and exposed area of the stud conductive layer as an encapsulating layer of material;   a third photo-resist materials developed on the surface area of the surface of the stud conductive layer encapsulating material;   a second electrically conductive layer developed on the stud conductive layer by removing at least one part of the layers of third photo-resist materials;   an isolation layer developed on the flat surface area of the surface of the stud conductive layer and the encapsulation material;   a conductive seed layer developed on grinded surface of the isolation layer and the second electrically conductive layer;   a fourth photo-resist materials developed on the conductive seed layer;   a third electrically conductive layer developed by removing at least one part of the layers of fourth photo-resist materials;   a masking layer developed on the third electrically conductive layer disposed on the conductive seed layer;   a solder mask or epoxy compound or polyimide compound layer developed by removing at least one part of the masking layer;   a fifth layer photo-resist material developed on the surface of the solder masked surface and bottom portion of the base; and   an opening on the patterned fifth layer photo-resist material located at bottom portion of the base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of the first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.   
     
     
         15 . The integrated circuit packaging according to  claim 14 , wherein the third electrically conductive layer is an etched layer of the conductive seed layer or third electrically conductive layer or any combination thereof by using etching process. 
     
     
         16 . The integrated circuit packaging according to  claim 14 , further include an interconnect on at least one side of the patterned conductive layer. 
     
     
         17 . The integrated circuit packaging according to  claim 14 , wherein the first patterned conductive layer has at least one trimmed surface. 
     
     
         18 . The integrated circuit packaging according to  claim 17 , wherein the trimmed surface of the first patterned conductive layer is trimmed by using chemical process, mechanical grinding process, laser trimming process, plasma etching or any combination thereof. 
     
     
         19 . The integrated circuit packaging according to  claim 14 , wherein the masking material is a mask set, photolithography material, masked pattern or any combination thereof. 
     
     
         20 . The integrated circuit packaging according to  claim 14 , wherein the base is selectively removed base, to form at least an internal opening and at least a positioning opening of the first patterned conductive layer exposed area. 
     
     
         21 . The integrated circuit packaging according to  claim 14 , wherein the base is selectively removed base, to form at least an internal opening and at least a positioning opening of the first patterned conductive layer exposed area, wherein the internal opening corresponds with an inside area of the first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer. 
     
     
         22 . The integrated circuit packaging according to  claim 14 , wherein the first patterned conductive layer and the second patterned conductive layer are disposed within the first patterned conductive layer, in which the other side of the first patterned conductive layer are located at the same plane with the second side of the second patterned conductive. 
     
     
         23 . The integrated circuit packaging according to  claim 14 , wherein the first patterned conductive layer are exposed to form at least an internal opening and at least a positioning opening by a selectively removing the base. 
     
     
         24 . The integrated circuit packaging according to  claim 14 , wherein the base is a selectively removed base that forms at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of the first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer. 
     
     
         25 . The integrated circuit package according to  claim 14 , wherein the positioning opening has a positioning mark, half-etched indentation, full-etched indentation patterns or any combination thereof on any one of the dielectric layer. 
     
     
         26 . The integrated circuit packaging according to  claims 14 , wherein the base is a charge carrier. 
     
     
         27 . The integrated circuit packaging according to  claim 14 , wherein the base etched using the masking material as a mask. 
     
     
         28 . The integrated circuit packaging according to  claim 14 , wherein the first patterned conductive layer is encapsulated. 
     
     
         29 . The integrated circuit packaging according to  claim 16 , wherein the interconnect is a metal finishing or organic finishing or any combination thereof.