Modular Integrated Circuit Chip Carrier

Abstract

An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

1 . A carrier comprising:
 a platform comprising a top surface with a first pattern of connection pads and a bottom surface with a second pattern of connection pads;   a first strut coupled to a first side of said bottom surface of said platform and said first strut comprising a first ball grid array; and   a second strut coupled to a second side of said bottom surface of said platform and said second strut comprising a second ball grid array;   wherein a connection pad of said first and second patterns of connection pads is coupled to at least one ball of said first and second ball grid arrays.   
     
     
         2 . The carrier of  claim 1  further comprising a first integrated circuit chip coupled to the top surface of said platform. 
     
     
         3 . The carrier of  claim 2  further comprising a second integrated circuit chip coupled to the bottom surface of said platform. 
     
     
         4 . The carrier of  claim 1  further comprising a second platform comprising a top surface with a third pattern of connection pads and a bottom surface with a fourth pattern of connection pads, wherein said first strut is coupled to said third pattern of connection pads on a first side of the top surface of said second platform and said second strut is coupled to said third pattern of connection pads on a second side of the top surface of said second platform. 
     
     
         5 . The carrier of  claim 1  wherein said platform further comprises:
 a plurality of layers including a routing layer; 
 a plurality of conductive paths wherein a conductive path is coupled with at least one pad of said patterns of connection pads; and 
 a plurality of platform vias. 
 
     
     
         6 . The carrier of  claim 5 , further comprising:
 a first strut via that extends up through said first strut from the bottom of said first strut to the top of said first strut, wherein said strut via connects to a conductive path in said platform; and   a second strut via that extends up through said second strut from the bottom of said second strut to the top of said second strut, wherein said strut via connects to a conductive path in said platform.   
     
     
         7 . An electronic circuit module comprising:
 a printed circuit board;   a platform comprising a top surface with a first pattern of connection pads and a bottom surface with a second pattern of connection pads;   a first strut coupled to a first side of said bottom surface of said platform and said first strut comprising a first ball grid array coupled to said printed circuit board; and   a second strut coupled to second side of said bottom surface of said platform and said second strut comprising a second ball grid array coupled to said printed circuit board;   wherein a connection pad of said first and second patterns of connection pads is coupled to at least one ball of said first and second ball grid arrays.   
     
     
         8 . The electronic circuit module of  claim 7  further comprising a first integrated circuit chip coupled to the top surface of said platform. 
     
     
         9 . The electronic circuit module of  claim 8  further comprising a second integrated circuit chip coupled to the bottom surface of said platform. 
     
     
         10 . The electronic circuit module of  claim 7  further comprising a second platform comprising a top surface with a third pattern of connection pads and a bottom surface with a fourth pattern of connection pads, wherein said first strut is coupled to said third pattern of connection pads on a first side of the top surface of said second platform and said second strut is coupled to said third pattern of connection pads on a second side of the top surface of said second platform. 
     
     
         11 . The electronic circuit module of  claim 7  wherein said platform further comprises:
 a plurality of layers including a routing layer; 
 a plurality of conductive paths wherein a conductive path is coupled with at least one pad of said patterns of connection pads; and 
 a plurality of platform vias. 
 
     
     
         12 . The electronic circuit module of  claim 11 , further comprising:
 a first strut via that extends up through said first strut from the bottom of said first strut to the top of said first strut, wherein said strut via connects to a conductive path in said platform; and   a second strut via that extends up through said second strut from the bottom of said second strut to the top of said second strut, wherein said strut via connects to a conductive path in said platform.   
     
     
         13 . The electronic circuit module of  claim 7 , wherein said printed circuit board has a width that is substantially the same as the width of said platform. 
     
     
         14 . A carrier comprising:
 a platform comprising a top surface with a first pattern of connection pads, a bottom surface with a second pattern of connection pads, and a plurality of conductive paths, at least one conductive path coupled to at least one pad of said patterns of connection pads;   a first strut coupled to a first side of said bottom surface of said platform and said first strut comprising a strut via that extends up through said first strut from the bottom of said first strut to the top of said first strut, said strut via connecting to a conductive path in said first platform; and   a second strut coupled to a second side of said bottom surface of said first platform and said second strut comprising a strut via that extends up through said second strut from the bottom of said second strut to the top of said second strut, said strut via connecting to a conductive path in said first platform.   
     
     
         15 . The carrier of  claim 14  further comprising a first integrated circuit chip coupled to the top surface of said platform. 
     
     
         16 . The carrier of  claim 15  further comprising a second integrated circuit chip coupled to the bottom surface of said platform. 
     
     
         17 . The carrier of  claim 14  further comprising a second platform comprising a top surface with a third pattern of connection pads and a bottom surface with a fourth pattern of connection pads, wherein said first strut is coupled to said third pattern of connection pads on a first side of the top surface of said second platform and said second strut is coupled to said third pattern of connection pads on a second side of the top surface of said second platform. 
     
     
         18 . The carrier of  claim 14  wherein said platform further comprises:
 a plurality of layers including a routing layer; and 
 a plurality of platform vias. 
 
     
     
         19 . The carrier of  claim 18 , wherein said platform vias are aligned with said strut vias. 
     
     
         20 . The carrier of  claim 18 , wherein said platform vias are staggered from said strut vias.