Inventor · disambiguated record
Uwe Griebenow
Also filed as: GRIEBENOW UWE
45 granted patents·12 pending applications·388 citations·filing 2007–2014
98Inventor score
Files withGRIEBENOW UWE14HOENTSCHEL JAN13GLOBALFOUNDRIES INC10SCHEIPER THILO6ADVANCED MICRO DEVICES INC5
Top patents by PatentIndex Score
57 records- 0198US7855118B2Drive current increase in transistors by asymmetric amorphization implantationADVANCED MICRO DEVICES INC·Filed 2009·Granted Dec 21, 2010·95 cites·20 claims
- 0297US8110487B2Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel regionGRIEBENOW UWE·Filed 2008·Granted Feb 7, 2012·104 cites·20 claims
- 0395US8247275B2Strain engineering in three-dimensional transistors based on globally strained semiconductor base layersHOENTSCHEL JAN·Filed 2010·Granted Aug 21, 2012·24 cites·16 claims
- 0491US8409942B2Replacement gate approach based on a reverse offset spacer applied prior to work function metal depositionSCHEIPER THILO·Filed 2010·Granted Apr 2, 2013·13 cites·20 claims
- 0590US8574991B2Asymmetric transistor devices formed by asymmetric spacers and tilted implantationHOENTSCHEL JAN·Filed 2012·Granted Nov 5, 2013·10 cites·13 claims
- 0690US8158482B2Asymmetric transistor devices formed by asymmetric spacers and tilted implantationHOENTSCHEL JAN·Filed 2009·Granted Apr 17, 2012·15 cites·12 claims
- 0788US8198152B2Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materialsBEYER SVEN·Filed 2010·Granted Jun 12, 2012·10 cites·14 claims
- 0887US8338894B2Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etchGRIEBENOW UWE·Filed 2010·Granted Dec 25, 2012·8 cites·19 claims
- 0985US7964970B2Technique for enhancing transistor performance by transistor specific contact designGLOBALFOUNDRIES INC·Filed 2007·Granted Jun 21, 2011·11 cites·17 claims
- 1084US8669151B2High-K metal gate electrode structures formed at different process stages of a semiconductor deviceHOENTSCHEL JAN·Filed 2010·Granted Mar 11, 2014·6 cites·17 claims
- 1184US8508008B2Optical signal transfer in a semiconductor device by using monolithic opto-electronic componentsGRIEBENOW UWE·Filed 2010·Granted Aug 13, 2013·10 cites·17 claims
- 1284US8426266B2Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devicesHOENTSCHEL JAN·Filed 2010·Granted Apr 23, 2013·6 cites·18 claims
- 1382US8455314B2Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stageGRIEBENOW UWE·Filed 2011·Granted Jun 4, 2013·5 cites·16 claims
- 1482US8329531B2Strain memorization in strained SOI substrates of semiconductor devicesHOENTSCHEL JAN·Filed 2010·Granted Dec 11, 2012·6 cites·14 claims
- 1581US9184095B2Contact bars with reduced fringing capacitance in a semiconductor deviceSCHEIPER THILO·Filed 2010·Granted Nov 10, 2015·6 cites·20 claims
- 1681US8470661B2High-K gate electrode structure formed after transistor fabrication by using a spacerFROHBERG KAI·Filed 2009·Granted Jun 25, 2013·8 cites·15 claims
- 1779US8615145B2Semiconductor device comprising a buried waveguide for device internal optical communicationGRIEBENOW UWE·Filed 2010·Granted Dec 24, 2013·2 cites·19 claims
- 1879US7871877B2Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel regionGLOBALFOUNDRIES INC·Filed 2008·Granted Jan 18, 2011·6 cites·18 claims
- 1978US8748281B2Enhanced confinement of sensitive materials of a high-K metal gate electrode structureHOENTSCHEL JAN·Filed 2010·Granted Jun 10, 2014·5 cites·1 claims
- 2073US8241973B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2008·Granted Aug 14, 2012·3 cites·16 claims
- 2172US8541885B2Technique for enhancing transistor performance by transistor specific contact designGERHARDT MARTIN·Filed 2011·Granted Sep 24, 2013·3 cites·8 claims
- 2272US8039342B2Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removalGLOBALFOUNDRIES INC·Filed 2010·Granted Oct 18, 2011·3 cites·21 claims
- 2371US8536036B2Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistorsBEYER SVEN·Filed 2010·Granted Sep 17, 2013·3 cites·20 claims
- 2471US8278174B2In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profileHOENTSCHEL JAN·Filed 2010·Granted Oct 2, 2012·3 cites·18 claims
- 2570US8440534B2Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2011·Granted May 14, 2013·2 cites·17 claims
- 2670US8318564B2Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantationSCHEIPER THILO·Filed 2010·Granted Nov 27, 2012·2 cites·17 claims
- 2769US8026134B2Recessed drain and source areas in combination with advanced silicide formation in transistorsADVANCED MICRO DEVICES INC·Filed 2009·Granted Sep 27, 2011·2 cites·18 claims
- 2868US8198633B2Stress transfer enhancement in transistors by a late gate re-crystallizationGRIEBENOW UWE·Filed 2009·Granted Jun 12, 2012·2 cites·23 claims
- 2968US8105962B2Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approachFROHBERG KAI·Filed 2008·Granted Jan 31, 2012·3 cites·7 claims
- 3066US8324039B2Reduced silicon thickness of N-channel transistors in SOI CMOS devicesGRIEBENOW UWE·Filed 2010·Granted Dec 4, 2012·2 cites·25 claims
- 3166US7887978B2Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditionsGLOBALFOUNDRIES INC·Filed 2008·Granted Feb 15, 2011·2 cites·15 claims
- 3265US8673713B2Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regionsHOENTSCHEL JAN·Filed 2011·Granted Mar 18, 2014·1 cites·15 claims
- 3364US8786027B2Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stageGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 22, 2014·1 cites·20 claims
- 3464US8450163B2Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approachBEYER SVEN·Filed 2010·Granted May 28, 2013·2 cites·19 claims
- 3560US8361844B2Method for adjusting the height of a gate electrode in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2010·Granted Jan 29, 2013·1 cites·20 claims
- 3659US8034669B2Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active regionADVANCED MICRO DEVICES INC·Filed 2009·Granted Oct 11, 2011·1 cites·17 claims
- 3755US9490189B2Semiconductor device comprising a stacked die configuration including an integrated peltier elementGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 8, 2016·0 cites·20 claims
- 3855US2009321841A1Cmos device comprising mos transistors with recessed drain and source areas and non-conformal metal silicide regionsHOENTSCHEL JAN·Filed 2009·Application pending·0 cites
- 3954US2009321850A1Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 4051US8883582B2High-K gate electrode structure formed after transistor fabrication by using a spacerADVANCED MICRO DEVICES INC·Filed 2013·Granted Nov 11, 2014·0 cites·17 claims
- 4151US8735237B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2012·Granted May 27, 2014·0 cites·22 claims
- 4249US8759960B2Semiconductor device comprising a stacked die configuration including an integrated Peltier elementGRIEBENOW UWE·Filed 2011·Granted Jun 24, 2014·0 cites·17 claims
- 4349US8017504B2Transistor having a high-k metal gate stack and a compressively stressed channelGLOBALFOUNDRIES INC·Filed 2009·Granted Sep 13, 2011·2 cites·12 claims
- 4447US2009108336A1Method for adjusting the height of a gate electrode in a semiconductor deviceFROHBERG KAI·Filed 2008·Application pending·0 cites
- 4546US2012091535A1Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner ApproachFROHBERG KAI·Filed 2011·Application pending·0 cites
- 4645US9054207B2Field effect transistors for a flash memory comprising a self-aligned charge storage regionGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 9, 2015·0 cites·21 claims
- 4745US8349744B2Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2008·Granted Jan 8, 2013·0 cites·13 claims
- 4845US2010078735A1Cmos device comprising nmos transistors and pmos transistors having increased strain-inducing sources and closely spaced metal silicide regionsHOENTSCHEL JAN·Filed 2009·Application pending·0 cites
- 4944US8426262B2Stress adjustment in stressed dielectric materials of semiconductor devices by stress relaxation based on radiationHOENTSCHEL JAN·Filed 2010·Granted Apr 23, 2013·0 cites·23 claims
- 5044US2009294809A1Reduction of metal silicide diffusion in a semiconductor device by protecting sidewalls of an active regionFROHBERG KAI·Filed 2009·Application pending·0 cites
Showing the top 50 of 57 patent records by PatentIndex Score.
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