Assignee
GRIEBENOW UWE
DE·11 granted patents·3 pending applications·138 citations·filing 2008–2012
Top patents by PatentIndex Score
14 records- 0197US8110487B2Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel regionGRIEBENOW UWE·Filed 2008·Granted Feb 7, 2012·104 cites·20 claims
- 0287US8338894B2Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etchGRIEBENOW UWE·Filed 2010·Granted Dec 25, 2012·8 cites·19 claims
- 0384US8508008B2Optical signal transfer in a semiconductor device by using monolithic opto-electronic componentsGRIEBENOW UWE·Filed 2010·Granted Aug 13, 2013·10 cites·17 claims
- 0482US8455314B2Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stageGRIEBENOW UWE·Filed 2011·Granted Jun 4, 2013·5 cites·16 claims
- 0579US8615145B2Semiconductor device comprising a buried waveguide for device internal optical communicationGRIEBENOW UWE·Filed 2010·Granted Dec 24, 2013·2 cites·19 claims
- 0673US8241973B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2008·Granted Aug 14, 2012·3 cites·16 claims
- 0770US8440534B2Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2011·Granted May 14, 2013·2 cites·17 claims
- 0868US8198633B2Stress transfer enhancement in transistors by a late gate re-crystallizationGRIEBENOW UWE·Filed 2009·Granted Jun 12, 2012·2 cites·23 claims
- 0966US8324039B2Reduced silicon thickness of N-channel transistors in SOI CMOS devicesGRIEBENOW UWE·Filed 2010·Granted Dec 4, 2012·2 cites·25 claims
- 1054US2009321850A1Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 1151US8735237B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2012·Granted May 27, 2014·0 cites·22 claims
- 1249US8759960B2Semiconductor device comprising a stacked die configuration including an integrated Peltier elementGRIEBENOW UWE·Filed 2011·Granted Jun 24, 2014·0 cites·17 claims
- 1344US2009294868A1Drive current adjustment for transistors formed in the same active region by locally inducing different lateral strain levels in the active regionGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 1444US2010025782A1Technique for reducing silicide non-uniformities in polysilicon gate electrodes by an intermediate diffusion blocking layerGRIEBENOW UWE·Filed 2009·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →