Assignee
HOENTSCHEL JAN
DE·21 granted patents·7 pending applications·151 citations·filing 2006–2012
Top patents by PatentIndex Score
28 records- 0196US8936977B2Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantationsHOENTSCHEL JAN·Filed 2012·Granted Jan 20, 2015·21 cites·14 claims
- 0296US8703578B2Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantationsHOENTSCHEL JAN·Filed 2012·Granted Apr 22, 2014·22 cites·15 claims
- 0395US8247275B2Strain engineering in three-dimensional transistors based on globally strained semiconductor base layersHOENTSCHEL JAN·Filed 2010·Granted Aug 21, 2012·24 cites·16 claims
- 0490US8574991B2Asymmetric transistor devices formed by asymmetric spacers and tilted implantationHOENTSCHEL JAN·Filed 2012·Granted Nov 5, 2013·10 cites·13 claims
- 0590US8158482B2Asymmetric transistor devices formed by asymmetric spacers and tilted implantationHOENTSCHEL JAN·Filed 2009·Granted Apr 17, 2012·15 cites·12 claims
- 0687US8154084B2Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon materialHOENTSCHEL JAN·Filed 2009·Granted Apr 10, 2012·12 cites·18 claims
- 0784US8669151B2High-K metal gate electrode structures formed at different process stages of a semiconductor deviceHOENTSCHEL JAN·Filed 2010·Granted Mar 11, 2014·6 cites·17 claims
- 0884US8426266B2Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devicesHOENTSCHEL JAN·Filed 2010·Granted Apr 23, 2013·6 cites·18 claims
- 0982US8329531B2Strain memorization in strained SOI substrates of semiconductor devicesHOENTSCHEL JAN·Filed 2010·Granted Dec 11, 2012·6 cites·14 claims
- 1079US8143133B2Technique for enhancing dopant profile and channel conductivity by millisecond anneal processesHOENTSCHEL JAN·Filed 2009·Granted Mar 27, 2012·5 cites·23 claims
- 1178US8748281B2Enhanced confinement of sensitive materials of a high-K metal gate electrode structureHOENTSCHEL JAN·Filed 2010·Granted Jun 10, 2014·5 cites·1 claims
- 1278US8450124B2Adjusting configuration of a multiple gate transistor by controlling individual finsHOENTSCHEL JAN·Filed 2009·Granted May 28, 2013·6 cites·24 claims
- 1378US8338885B2Technique for enhancing dopant profile and channel conductivity by millisecond anneal processesHOENTSCHEL JAN·Filed 2012·Granted Dec 25, 2012·3 cites·14 claims
- 1476US8772878B2Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon materialHOENTSCHEL JAN·Filed 2012·Granted Jul 8, 2014·3 cites·21 claims
- 1572US8062952B2Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistorsHOENTSCHEL JAN·Filed 2010·Granted Nov 22, 2011·3 cites·22 claims
- 1671US8278174B2In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profileHOENTSCHEL JAN·Filed 2010·Granted Oct 2, 2012·3 cites·18 claims
- 1765US8673713B2Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regionsHOENTSCHEL JAN·Filed 2011·Granted Mar 18, 2014·1 cites·15 claims
- 1855US2009321841A1Cmos device comprising mos transistors with recessed drain and source areas and non-conformal metal silicide regionsHOENTSCHEL JAN·Filed 2009·Application pending·0 cites
- 1949US2010025743A1Transistor with embedded si/ge material having enhanced boron confinementHOENTSCHEL JAN·Filed 2009·Application pending·0 cites
- 2045US2010078735A1Cmos device comprising nmos transistors and pmos transistors having increased strain-inducing sources and closely spaced metal silicide regionsHOENTSCHEL JAN·Filed 2009·Application pending·0 cites
- 2144US8426262B2Stress adjustment in stressed dielectric materials of semiconductor devices by stress relaxation based on radiationHOENTSCHEL JAN·Filed 2010·Granted Apr 23, 2013·0 cites·23 claims
- 2244US2007123010A1Technique for reducing crystal defects in strained transistors by tilted preamorphizationHOENTSCHEL JAN·Filed 2006·Application pending·0 cites
- 2344US2009218633A1Cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areasHOENTSCHEL JAN·Filed 2008·Application pending·0 cites
- 2441US2014103449A1Oxygen free rta on gate first hkmg stacksHOENTSCHEL JAN·Filed 2012·Application pending·0 cites
- 2540US2013292774A1Method for forming a semiconductor device having raised drain and source regions and corresponding semiconductor deviceHOENTSCHEL JAN·Filed 2012·Application pending·0 cites
- 2639US8440530B2Methods of forming highly scaled semiconductor devices using a disposable spacer techniqueHOENTSCHEL JAN·Filed 2011·Granted May 14, 2013·0 cites·19 claims
- 2739US8143132B2Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regimeHOENTSCHEL JAN·Filed 2010·Granted Mar 27, 2012·0 cites·10 claims
- 2838US8664068B2Low-diffusion drain and source regions in CMOS transistors for low power/high performance applicationsHOENTSCHEL JAN·Filed 2011·Granted Mar 4, 2014·0 cites·19 claims
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