Inventor · disambiguated record
Torsten Huisinga
Also filed as: HUISINGA TORSTEN
19 granted patents·9 pending applications·50 citations·filing 2010–2016
92Inventor score
Top patents by PatentIndex Score
28 records- 0187US8598714B2Semiconductor device comprising through hole vias having a stress relaxation mechanismHUISINGA TORSTEN·Filed 2010·Granted Dec 3, 2013·11 cites·21 claims
- 0285US8399335B2Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal featuresHUISINGA TORSTEN·Filed 2010·Granted Mar 19, 2013·9 cites·18 claims
- 0381US7985668B1Method for forming a metal silicide having a lower potential for containing material defectsGLOBALFOUNDRIES INC·Filed 2010·Granted Jul 26, 2011·6 cites·18 claims
- 0476US8216928B1Methods for fabricating semiconductor devices having local contactsRICHTER RALF·Filed 2011·Granted Jul 10, 2012·4 cites·20 claims
- 0575US8786088B2Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interactionHUISINGA TORSTEN·Filed 2010·Granted Jul 22, 2014·4 cites·12 claims
- 0672US9305878B2Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnectsGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 5, 2016·2 cites·19 claims
- 0771US8536050B2Selective shrinkage of contact elements in a semiconductor deviceFROHBERG KAI·Filed 2011·Granted Sep 17, 2013·3 cites·18 claims
- 0870US8932911B2Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnectsGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 13, 2015·2 cites·19 claims
- 0967US8859418B2Methods of forming conductive structures using a dual metal hard mask techniqueHUISINGA TORSTEN·Filed 2012·Granted Oct 14, 2014·2 cites·16 claims
- 1066US9257329B2Methods for fabricating integrated circuits including densifying interlevel dielectric layersGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 9, 2016·2 cites·19 claims
- 1166US8492269B2Hybrid contact structure with low aspect ratio contacts in a semiconductor deviceHEINRICH JENS·Filed 2011·Granted Jul 23, 2013·2 cites·15 claims
- 1266US8383510B2Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materialsGLOBALFOUNDRIES INC·Filed 2011·Granted Feb 26, 2013·2 cites·17 claims
- 1360US8435841B2Enhancement of ultraviolet curing of tensile stress liner using reflective materialsRICHTER RALF·Filed 2010·Granted May 7, 2013·1 cites·12 claims
- 1455US9478602B2Method of forming an embedded metal-insulator-metal (MIM) capacitorGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 25, 2016·0 cites·7 claims
- 1550US9685497B2Embedded metal-insulator-metal capacitorGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 20, 2017·0 cites·14 claims
- 1643US9287109B2Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processesGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 15, 2016·0 cites·20 claims
- 1743US2015076559A1Integrated circuits with strained silicon and methods for fabricating such circuitsGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 1841US8324108B2Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistryRICHTER RALF·Filed 2011·Granted Dec 4, 2012·0 cites·20 claims
- 1940US8922023B2Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materialsHEINRICH JENS·Filed 2013·Granted Dec 30, 2014·0 cites·15 claims
- 2040US8673770B2Methods of forming conductive structures in dielectric layers on an integrated circuit deviceHUISINGA TORSTEN·Filed 2011·Granted Mar 18, 2014·0 cites·22 claims
- 2139US2013302989A1Reducing line edge roughness in hardmask integration schemesKENNY OISIN·Filed 2012·Application pending·0 cites
- 2238US2012235304A1Ultraviolet (uv)-reflecting film for beol processingHUISINGA TORSTEN·Filed 2011·Application pending·0 cites
- 2337US2013108779A1Methods of Filling Voids in Copper StructuresHUISINGA TORSTEN·Filed 2011·Application pending·0 cites
- 2437US2013302974A1Replacement gate electrode fill at reduced temperaturesHAHN JENS·Filed 2012·Application pending·0 cites
- 2537US2012153405A1Semiconductor Device Comprising a Contact Structure with Reduced Parasitic CapacitanceHEINRICH JENS·Filed 2011·Application pending·0 cites
- 2637US2013189822A1Methods of fabricating integrated circuits with the elimination of voids in interlayer dielecticsFROHBERG KAI·Filed 2012·Application pending·0 cites
- 2736US2012199980A1Integrated circuits having interconnect structures and methods for fabricating integrated circuits having interconnect structuresPFUETZNER EGON R·Filed 2011·Application pending·0 cites
- 2836US2014349479A1Method including a removal of a hardmask from a semiconductor structure and rinsing the semiconductor structure with an alkaline rinse solutionGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →