Inventor · disambiguated record
Joonyoung Choi
Also filed as: CHOI JOONYOUNG
15 granted patents·5 pending applications·46 citations·filing 2003–2024
89Inventor score
Files withSAMSUNG ELECTRONICS CO LTD5CHOI JOONYOUNG4STATS CHIPPAC LTD4CHOI DAESIK2STATS CHIPPAC PTE LTD2
Top patents by PatentIndex Score
20 records- 0190US8288203B2Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bumpCHO SUNGWON·Filed 2011·Granted Oct 16, 2012·12 cites·20 claims
- 0280US8835301B2Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor waferCHOI JOONYOUNG·Filed 2011·Granted Sep 16, 2014·5 cites·25 claims
- 0379US8546194B2Integrated circuit packaging system with interconnects and method of manufacture thereofCHOI JOONYOUNG·Filed 2011·Granted Oct 1, 2013·6 cites·20 claims
- 0473US8994048B2Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integrationCHOI JOONYOUNG·Filed 2010·Granted Mar 31, 2015·4 cites·29 claims
- 0573US7321602B2Apparatus and method for inserting null packet in digital broadcasting transmission systemKOREA ELECTRONICS TELECOMM·Filed 2003·Granted Jan 22, 2008·14 cites·8 claims
- 0670US2024128330A1Integrated circuit devices and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 0766US8642469B2Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor waferCHOI DAESIK·Filed 2011·Granted Feb 4, 2014·2 cites·31 claims
- 0865US11888038B2Integrated circuit devices and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Jan 30, 2024·0 cites·19 claims
- 0963US9780063B2Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor waferSTATS CHIPPAC LTD·Filed 2014·Granted Oct 3, 2017·1 cites·5 claims
- 1059US9524958B2Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bondingSTATS CHIPPAC LTD·Filed 2013·Granted Dec 20, 2016·1 cites·26 claims
- 1157US11171038B2Fabrication method of integrated circuit semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Nov 9, 2021·0 cites·20 claims
- 1256US2024400398A1Method of recycling silicon wastewater and method of manufacturing semiconductor by using the sameSAMSUNG ELECTRONICS CO LTD·Filed 2024·Application pending·0 cites
- 1355US12331983B2RefrigeratorLG ELECTRONICS INC·Filed 2021·Granted Jun 17, 2025·0 cites·20 claims
- 1454US8343853B2Semiconductor wafer, semiconductor device using the same, and method and apparatus for producing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Jan 1, 2013·1 cites·7 claims
- 1553US2024021566A1Semiconductor Device and Method of Forming Underfill Dam for Chip-to-Wafer DeviceSTATS CHIPPAC PTE LTD·Filed 2022·Application pending·0 cites
- 1652US9252093B2Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor waferSTATS CHIPPAC LTD·Filed 2013·Granted Feb 2, 2016·0 cites·25 claims
- 1749US2023411346A1Semiconductor device and method for making the sameSTATS CHIPPAC PTE LTD·Filed 2023·Application pending·0 cites
- 1848US2013001773A1Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed BumpSTATS CHIPPAC LTD·Filed 2012·Application pending·0 cites
- 1947US9093278B1Method of manufacture of integrated circuit packaging system with plasma processingCHOI JOONYOUNG·Filed 2013·Granted Jul 28, 2015·0 cites·20 claims
- 2043US9059108B2Integrated circuit packaging system with interconnectsCHOI DAESIK·Filed 2012·Granted Jun 16, 2015·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →