Assignee
STATS CHIPPAC LTD
SG·711 granted patents·50 pending applications·10,630 citations·filing 2004–2016
Top patents by PatentIndex Score
761 records- 0199US8980691B2Semiconductor device and method of forming low profile 3D fan-out packageSTATS CHIPPAC LTD·Filed 2013·Granted Mar 17, 2015·98 cites·35 claims
- 0299US8354297B2Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor dieSTATS CHIPPAC LTD·Filed 2010·Granted Jan 15, 2013·125 cites·25 claims
- 0399US8039303B2Method of forming stress relief layer between die and interconnect structureSTATS CHIPPAC LTD·Filed 2009·Granted Oct 18, 2011·110 cites·25 claims
- 0499US7928552B1Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2010·Granted Apr 19, 2011·110 cites·10 claims
- 0599US7517733B2Leadframe design for QFN package with top terminal leadsSTATS CHIPPAC LTD·Filed 2007·Granted Apr 14, 2009·125 cites·22 claims
- 0699US7429786B2Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sidesSTATS CHIPPAC LTD·Filed 2006·Granted Sep 30, 2008·177 cites·15 claims
- 0799US7364945B2Method of mounting an integrated circuit package in an encapsulant cavitySTATS CHIPPAC LTD·Filed 2006·Granted Apr 29, 2008·100 cites·13 claims
- 0899US7354800B2Method of fabricating a stacked integrated circuit package systemSTATS CHIPPAC LTD·Filed 2006·Granted Apr 8, 2008·119 cites·17 claims
- 0998US9893045B2Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnectSTATS CHIPPAC LTD·Filed 2015·Granted Feb 13, 2018·33 cites·19 claims
- 1098US9786623B2Semiconductor device and method of forming PoP semiconductor device with RDL over top packageSTATS CHIPPAC LTD·Filed 2015·Granted Oct 10, 2017·37 cites·25 claims
- 1198US9443797B2Semiconductor device having wire studs as vertical interconnect in FO-WLPSTATS CHIPPAC LTD·Filed 2013·Granted Sep 13, 2016·55 cites·16 claims
- 1298US9362161B2Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor packageSTATS CHIPPAC LTD·Filed 2014·Granted Jun 7, 2016·47 cites·23 claims
- 1398US9064936B2Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPSTATS CHIPPAC LTD·Filed 2013·Granted Jun 23, 2015·58 cites·12 claims
- 1498US9059186B2Embedded semiconductor die package and method of making the same using metal frame carrierSTATS CHIPPAC LTD·Filed 2014·Granted Jun 16, 2015·41 cites·25 claims
- 1598US8994185B2Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSPSTATS CHIPPAC LTD·Filed 2013·Granted Mar 31, 2015·44 cites·35 claims
- 1698US8354304B2Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulantSTATS CHIPPAC LTD·Filed 2008·Granted Jan 15, 2013·69 cites·25 claims
- 1798US8349735B2Semiconductor device and method of forming conductive TSV with insulating annular ringSTATS CHIPPAC LTD·Filed 2010·Granted Jan 8, 2013·44 cites·25 claims
- 1898US8039304B2Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structuresSTATS CHIPPAC LTD·Filed 2009·Granted Oct 18, 2011·60 cites·20 claims
- 1998US8008121B2Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrateSTATS CHIPPAC LTD·Filed 2009·Granted Aug 30, 2011·105 cites·13 claims
- 2098US7973406B2Bump-on-lead flip chip interconnectionSTATS CHIPPAC LTD·Filed 2010·Granted Jul 5, 2011·31 cites·23 claims
- 2198US7955942B2Semiconductor device and method of forming a 3D inductor from prefabricated pillar frameSTATS CHIPPAC LTD·Filed 2009·Granted Jun 7, 2011·57 cites·13 claims
- 2298US7923295B2Semiconductor device and method of forming the device using sacrificial carrierSTATS CHIPPAC LTD·Filed 2009·Granted Apr 12, 2011·55 cites·14 claims
- 2398US7902644B2Integrated circuit package system for electromagnetic isolationSTATS CHIPPAC LTD·Filed 2007·Granted Mar 8, 2011·95 cites·18 claims
- 2498US7858441B2Semiconductor package with semiconductor core structure and method of forming sameSTATS CHIPPAC LTD·Filed 2008·Granted Dec 28, 2010·75 cites·23 claims
- 2598US7838337B2Semiconductor device and method of forming an interposer package with through silicon viasSTATS CHIPPAC LTD·Filed 2008·Granted Nov 23, 2010·166 cites·20 claims
- 2698US7799602B2Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structureSTATS CHIPPAC LTD·Filed 2008·Granted Sep 21, 2010·72 cites·20 claims
- 2798US7772046B2Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interferenceSTATS CHIPPAC LTD·Filed 2008·Granted Aug 10, 2010·81 cites·19 claims
- 2898US7741156B2Semiconductor device and method of forming through vias with reflowed conductive materialSTATS CHIPPAC LTD·Filed 2008·Granted Jun 22, 2010·59 cites·8 claims
- 2998US7642128B1Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPSTATS CHIPPAC LTD·Filed 2008·Granted Jan 5, 2010·144 cites·20 claims
- 3098US7629860B2Miniaturized wide-band baluns for RF applicationsSTATS CHIPPAC LTD·Filed 2007·Granted Dec 8, 2009·61 cites·31 claims
- 3198US7618846B1Semiconductor device and method of forming shielding along a profile disposed in peripheral region around the deviceSTATS CHIPPAC LTD·Filed 2008·Granted Nov 17, 2009·92 cites·19 claims
- 3298US7553752B2Method of making a wafer level integration packageSTATS CHIPPAC LTD·Filed 2007·Granted Jun 30, 2009·79 cites·17 claims
- 3398US7537962B2Method of fabricating a shielded stacked integrated circuit package systemSTATS CHIPPAC LTD·Filed 2006·Granted May 26, 2009·78 cites·18 claims
- 3498US7435619B2Method of fabricating a 3-D package stacking systemSTATS CHIPPAC LTD·Filed 2006·Granted Oct 14, 2008·75 cites·20 claims
- 3598US7429787B2Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sidesSTATS CHIPPAC LTD·Filed 2006·Granted Sep 30, 2008·88 cites·17 claims
- 3698US7394148B2Module having stacked chip scale semiconductor packagesSTATS CHIPPAC LTD·Filed 2006·Granted Jul 1, 2008·74 cites·13 claims
- 3798US7372141B2Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sidesSTATS CHIPPAC LTD·Filed 2006·Granted May 13, 2008·109 cites·24 claims
- 3898US7288835B2Integrated circuit package-in-package systemSTATS CHIPPAC LTD·Filed 2006·Granted Oct 30, 2007·135 cites·17 claims
- 3997US9941207B2Semiconductor device and method of fabricating 3D package with short cycle time and high yieldSTATS CHIPPAC LTD·Filed 2015·Granted Apr 10, 2018·26 cites·23 claims
- 4097US9842798B2Semiconductor device and method of forming a PoP device with embedded vertical interconnect unitsSTATS CHIPPAC LTD·Filed 2013·Granted Dec 12, 2017·31 cites·6 claims
- 4197US9837484B2Semiconductor device and method of forming substrate including embedded component with symmetrical structureSTATS CHIPPAC LTD·Filed 2015·Granted Dec 5, 2017·31 cites·24 claims
- 4297US9548240B2Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor packageSTATS CHIPPAC LTD·Filed 2015·Granted Jan 17, 2017·20 cites·25 claims
- 4397US9349700B2Semiconductor device and method of forming stress-reduced conductive joint structuresSTATS CHIPPAC LTD·Filed 2014·Granted May 24, 2016·63 cites·14 claims
- 4497US8896109B2Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor dieSTATS CHIPPAC LTD·Filed 2012·Granted Nov 25, 2014·39 cites·24 claims
- 4597US8354746B2Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulantSTATS CHIPPAC LTD·Filed 2011·Granted Jan 15, 2013·34 cites·26 claims
- 4697US8021907B2Method and apparatus for thermally enhanced semiconductor packageSTATS CHIPPAC LTD·Filed 2008·Granted Sep 20, 2011·43 cites·18 claims
- 4797US8004095B2Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerSTATS CHIPPAC LTD·Filed 2010·Granted Aug 23, 2011·50 cites·25 claims
- 4897US7993972B2Wafer level die integration and method thereforSTATS CHIPPAC LTD·Filed 2008·Granted Aug 9, 2011·46 cites·21 claims
- 4997US7989270B2Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitorsSTATS CHIPPAC LTD·Filed 2009·Granted Aug 2, 2011·45 cites·24 claims
- 5097US7923304B2Integrated circuit packaging system with conductive pillars and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Apr 12, 2011·61 cites·4 claims
Showing the top 50 of 761 patent records by PatentIndex Score.
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