Inventor · disambiguated record
Eng Hua Lim
Also filed as: LIM ENG H · LIM ENG-HUA
26 granted patents·5 pending applications·822 citations·filing 1998–2009
97Inventor score
Top patents by PatentIndex Score
31 records- 0193US6664156B1Method for forming L-shaped spacers with precise width controlCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·76 cites·17 claims
- 0293US6632712B1Method of fabricating variable length vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 14, 2003·89 cites·31 claims
- 0392US6228727B1Method to form shallow trench isolations with rounded corners and reduced trench oxide recessCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted May 8, 2001·142 cites·18 claims
- 0490US6468851B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 22, 2002·55 cites·39 claims
- 0588US6350661B2Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Feb 26, 2002·49 cites·5 claims
- 0684US6762085B2Method of forming a high performance and low cost CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 13, 2004·36 cites·27 claims
- 0784US6265302B1Partially recessed shallow trench isolation method for fabricating borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 24, 2001·77 cites·17 claims
- 0882US6165871AMethod of making low-leakage architecture for sub-0.18 μm salicided CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 26, 2000·55 cites·26 claims
- 0975US7545004B2Method and structure for forming strained devicesIBM·Filed 2005·Granted Jun 9, 2009·6 cites·4 claims
- 1074US6271133B1Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabricationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 7, 2001·36 cites·6 claims
- 1173US6664153B2Method to fabricate a single gate with dual work-functionsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·18 cites·22 claims
- 1273US6429109B1Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gateCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 6, 2002·18 cites·35 claims
- 1372US6841441B2Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jan 11, 2005·12 cites·37 claims
- 1471US6653227B1Method of cobalt silicidation using an oxide-Titanium interlayerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 25, 2003·21 cites·21 claims
- 1571US6610575B1Forming dual gate oxide thickness on vertical transistors by ion implantationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·16 cites·47 claims
- 1668US6632745B1Method of forming almost L-shaped spacer for improved ILD gap fillCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 14, 2003·20 cites·45 claims
- 1768US6605501B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 12, 2003·14 cites·36 claims
- 1866US8148221B2Double anneal with improved reliability for dual contact etch stop liner schemeLIM KHEE YONG·Filed 2009·Granted Apr 3, 2012·3 cites·34 claims
- 1966US5956137AIn-line process monitoring using micro-raman spectroscopyCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Sep 21, 1999·31 cites·20 claims
- 2062US6610604B1Method of forming small transistor gates by using self-aligned reverse spacer as a hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·10 cites·30 claims
- 2161US7615433B2Double anneal with improved reliability for dual contact etch stop liner schemeCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 10, 2009·1 cites·25 claims
- 2261US7396724B2Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicalsIBM·Filed 2005·Granted Jul 8, 2008·2 cites·18 claims
- 2358US6383922B1Thermal stability improvement of CoSi2 film by stuffing in titaniumCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 7, 2002·8 cites·21 claims
- 2458US6297126B1Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 2, 2001·20 cites·11 claims
- 2554US6544848B1Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacersCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 8, 2003·6 cites·25 claims
- 2647US6828082B2Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 7, 2004·1 cites·51 claims
- 2743US2005089777A1Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 2843US2005101083A1Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 2940US2008026523A1Structure and method to implement dual stressor layers with improved silicide controlCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 3038US2004266155A1Formation of small gates beyond lithographic limitsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 3135US2006079046A1Method and structure for improving cmos device reliability using combinations of insulating materialsIBM·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →