Inventor · disambiguated record
James Walter Blatchford
Also filed as: BLATCHFORD JAMES · BLATCHFORD JAMES W · BLATCHFORD JAMES WALTER · BLATCHFORD JR JAMES W
54 granted patents·8 pending applications·392 citations·filing 1998–2020
98Inventor score
Files withTEXAS INSTRUMENTS INC42BLATCHFORD JAMES WALTER11AGERE SYST GUARDIAN CORP1AGERE SYSTEMS INC1BALDWIN GREGORY CHARLES1
Top patents by PatentIndex Score
62 records- 0196US6970233B2System and method for custom-polarized photolithography illuminationTEXAS INSTRUMENTS INC·Filed 2003·Granted Nov 29, 2005·74 cites·4 claims
- 0292US7569309B2Gate critical dimension variation by use of ghost featuresTEXAS INSTRUMENTS INC·Filed 2005·Granted Aug 4, 2009·104 cites·6 claims
- 0391US8707223B2Method for ensuring DPT compliance with autorouted metal layersTEXAS INSTRUMENTS INC·Filed 2012·Granted Apr 22, 2014·16 cites·12 claims
- 0490US8756550B2Method to ensure double patterning technology compliance in standard cellsTEXAS INSTRUMENTS INC·Filed 2012·Granted Jun 17, 2014·13 cites·4 claims
- 0587US8372743B2Hybrid pitch-split pattern-split lithography processTEXAS INSTRUMENTS INC·Filed 2012·Granted Feb 12, 2013·9 cites·17 claims
- 0687US6680150B2Suppression of side-lobe printing by shape engineeringAGERE SYSTEMS INC·Filed 2001·Granted Jan 20, 2004·27 cites·42 claims
- 0786US9812452B2Method to form silicide and contact at embedded epitaxial facetTEXAS INSTRUMENTS INC·Filed 2016·Granted Nov 7, 2017·4 cites·17 claims
- 0885US7930656B2System and method for making photomasksTEXAS INSTRUMENTS INC·Filed 2007·Granted Apr 19, 2011·8 cites·11 claims
- 0984US9305848B2Elongated contacts using litho-freeze-litho-etch processTEXAS INSTRUMENTS INC·Filed 2014·Granted Apr 5, 2016·4 cites·20 claims
- 1081US9620419B2Elongated contacts using litho-freeze-litho-etch processTEXAS INSTRUMENTS INC·Filed 2016·Granted Apr 11, 2017·2 cites·8 claims
- 1181US8461038B2Two-track cross-connects in double-patterned metal layers using a forbidden zoneBLATCHFORD JAMES WALTER·Filed 2012·Granted Jun 11, 2013·5 cites·16 claims
- 1281US7737016B2Two-print two-etch method for enhancement of CD control using ghost polyTEXAS INSTRUMENTS INC·Filed 2006·Granted Jun 15, 2010·7 cites·10 claims
- 1378US9899364B2Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the twoTEXAS INSTRUMENTS INC·Filed 2015·Granted Feb 20, 2018·2 cites·16 claims
- 1477US7745067B2Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirementsTEXAS INSTRUMENTS INC·Filed 2005·Granted Jun 29, 2010·4 cites·32 claims
- 1576US8176443B2Layout of printable assist features to aid transistor controlRATHSACK BENJAMEN MICHAEL·Filed 2008·Granted May 8, 2012·8 cites·8 claims
- 1675US8575020B2Pattern-split decomposition strategy for double-patterned lithography processBLATCHFORD JAMES WALTER·Filed 2012·Granted Nov 5, 2013·3 cites·10 claims
- 1774US9312170B2Metal on elongated contactsTEXAS INSTRUMENTS INC·Filed 2014·Granted Apr 12, 2016·2 cites·14 claims
- 1874US6258610B1Method analyzing a semiconductor surface using line width metrology with auto-correlation operationAGERE SYST GUARDIAN CORP·Filed 1999·Granted Jul 10, 2001·45 cites·12 claims
- 1973US11974421B2SRAM layout for double patterningTEXAS INSTRUMENTS INC·Filed 2020·Granted Apr 30, 2024·0 cites·18 claims
- 2073US10043714B2Elongated contacts using litho-freeze-litho-etch processTEXAS INSTRUMENTS INC·Filed 2017·Granted Aug 7, 2018·1 cites·14 claims
- 2170US9024450B2Two-track cross-connect in double-patterned structure using rectangular viaTEXAS INSTRUMENTS INC·Filed 2013·Granted May 5, 2015·2 cites·1 claims
- 2270US7807343B2EDA methodology for extending ghost feature beyond notched active to improve adjacent gate CD control using a two-print-two-etch approachTEXAS INSTRUMENTS INC·Filed 2007·Granted Oct 5, 2010·3 cites·15 claims
- 2369US10103171B2Metal on elongated contactsTEXAS INSTRUMENTS INC·Filed 2016·Granted Oct 16, 2018·1 cites·11 claims
- 2469US8828833B1System for controlling SiGe-to-gate spacingTEXAS INSTRUMENTS INC·Filed 2013·Granted Sep 9, 2014·2 cites·10 claims
- 2568US9112000B2Method for ensuring DPT compliance for auto-routed via layersTEXAS INSTRUMENTS INC·Filed 2012·Granted Aug 18, 2015·2 cites·6 claims
- 2668US8569838B2Control of local environment for polysilicon conductors in integrated circuitsBLATCHFORD JR JAMES WALTER·Filed 2011·Granted Oct 29, 2013·3 cites·10 claims
- 2766US7790525B2Method of achieving dense-pitch interconnect patterning in integrated circuitsTEXAS INSTRUMENTS INC·Filed 2007·Granted Sep 7, 2010·2 cites·10 claims
- 2864US10840250B2SRAM layout for double patterningTEXAS INSTRUMENTS INC·Filed 2018·Granted Nov 17, 2020·0 cites·12 claims
- 2964US8667432B2Gate CD control using local design on both sides of neighboring dummy gate level featuresTEXAS INSTRUMENTS INC·Filed 2013·Granted Mar 4, 2014·1 cites·4 claims
- 3063US8603905B2Dual alignment strategy for optimizing contact layer alignmentBLATCHFORD JAMES WALTER·Filed 2009·Granted Dec 10, 2013·2 cites·19 claims
- 3163US8455180B2Gate CD control using local design on both sides of neighboring dummy gate level featuresBLATCHFORD JAMES WALTER·Filed 2010·Granted Jun 4, 2013·1 cites·7 claims
- 3262US8584053B2Manufacturability enhancements for gate patterning process using polysilicon sub layerBLATCHFORD JAMES WALTER·Filed 2011·Granted Nov 12, 2013·1 cites·15 claims
- 3362US8580675B2Two-track cross-connect in double-patterned structure using rectangular viaBLATCHFORD JAMES WALTER·Filed 2012·Granted Nov 12, 2013·1 cites·14 claims
- 3462US7300883B2Method for patterning sub-lithographic features in semiconductor manufacturingTEXAS INSTRUMENTS INC·Filed 2004·Granted Nov 27, 2007·8 cites·19 claims
- 3561US8304317B2Gate line edge roughness reduction by using 2P/2E process together with high temperature bakeGU YIMING·Filed 2009·Granted Nov 6, 2012·2 cites·18 claims
- 3658US8745548B2Perturbational technique for co-optimizing design rules and illumination conditions for lithography processTEXAS INSTRUMENTS INC·Filed 2013·Granted Jun 3, 2014·0 cites·10 claims
- 3757US10103153B2SRAM layout for double patterningTEXAS INSTRUMENTS INC·Filed 2015·Granted Oct 16, 2018·0 cites·8 claims
- 3857US9508601B2Method to form silicide and contact at embedded epitaxial facetTEXAS INSTRUMENTS INC·Filed 2014·Granted Nov 29, 2016·0 cites·19 claims
- 3957US8513105B2Flexible integration of logic blocks with transistors of different threshold voltagesBALDWIN GREGORY CHARLES·Filed 2010·Granted Aug 20, 2013·1 cites·14 claims
- 4057US6934930B2Generating an optical model for lens aberrationsTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 23, 2005·7 cites·17 claims
- 4156US10181474B2SRAM layout for double patterningTEXAS INSTRUMENTS INC·Filed 2012·Granted Jan 15, 2019·0 cites·6 claims
- 4255US10008499B2Method to form silicide and contact at embedded epitaxial facetTEXAS INSTRUMENTS INC·Filed 2017·Granted Jun 26, 2018·0 cites·17 claims
- 4354US8663879B2Gate CD control using local design on both sides of neighboring dummy gate level featuresTEXAS INSTRUMENTS INC·Filed 2013·Granted Mar 4, 2014·0 cites·4 claims
- 4451US9123562B2Layout method to minimize context effects and die areaTEXAS INSTRUMENTS INC·Filed 2012·Granted Sep 1, 2015·0 cites·9 claims
- 4551US2014183663A1Raised Source/Drain MOS Transistor and Method of Forming the Transistor with an Implant Spacer and an Epitaxial SpacerTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
- 4650US8607170B2Perturbational technique for co-optimizing design rules and illumination conditions for lithography processBLATCHFORD JAMES WALTER·Filed 2012·Granted Dec 10, 2013·0 cites·20 claims
- 4750US6200734B1Method for fabricating semiconductor devicesLUCENT TECHNOLOGIES INC·Filed 1998·Granted Mar 13, 2001·15 cites·14 claims
- 4850US2010167472A1Implantation shadowing effect reduction using thermal bake processTEXAS INSTRUMENTS INC·Filed 2009·Application pending·0 cites
- 4949US8703608B2Control of local environment for polysilicon conductors in integrated circuitsTEXAS INSTRUMENTS INC·Filed 2013·Granted Apr 22, 2014·0 cites·10 claims
- 5049US8051391B2Method for layout of random via arrays in the presence of strong pitch restrictionsTEXAS INSTRUMENTS INC·Filed 2008·Granted Nov 1, 2011·0 cites·11 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when James Walter Blatchford files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →