Raised Source/Drain MOS Transistor and Method of Forming the Transistor with an Implant Spacer and an Epitaxial Spacer

Abstract

A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor region having a conductivity type;   a source having a conductivity type that is opposite to the conductivity type of the semiconductor region, and including a lightly-doped source region that touches the semiconductor region, a heavily-doped source region that touches the lightly-doped source region, and a raised source region that touches the heavily-doped source region, the heavily-doped source region having a width, the raised source region having a width, the width of the raised source region being greater than the width of the heavily-doped source region;   a drain having a conductivity type that is opposite to the conductivity type of the semiconductor region, and including a lightly-doped drain region that touches the semiconductor region, a heavily-doped drain region that touches the lightly-doped drain region, and a raised drain region that touches the heavily-doped drain region;   a channel region of the semiconductor region lying laterally between the source and the drain;   a gate dielectric touching and lying over the channel region; and   a gate touching and lying over the gate dielectric.   
     
     
         2 . The semiconductor structure of  claim 1  and further comprising a sidewall spacer being non-conductive, touching the raised source region and the raised drain region, and laterally surrounding the gate. 
     
     
         3 . The semiconductor structure of  claim 2  wherein the sidewall spacer touches and lies over a top surface of the raised source region. 
     
     
         4 . The semiconductor structure of  claim 3  wherein a maximum width of the sidewall spacer is substantially greater than a minimum distance that separates the raised source region from the gate. 
     
     
         5 . The semiconductor structure of  claim 1  wherein a top surface of the raised source region and a top surface of the raised drain region lie in a plane that passes through the gate, the plane lying above a bottom surface of the gate. 
     
     
         6 . A semiconductor structure comprising:
 a semiconductor region having a conductivity type;   a source having a conductivity type that is opposite to the conductivity type of the semiconductor region, and including a lightly-doped source region that touches the semiconductor region, a heavily-doped source region that touches the lightly-doped source region, and a raised source region that touches the heavily-doped source region, the heavily-doped source region having a width, the raised source region having a width, the width of the heavily-doped source region being substantially greater than the width of the raised source region;   a drain having a conductivity type that is opposite to the conductivity type of the semiconductor region, and including a lightly-doped drain region that touches the semiconductor region, a heavily-doped drain region that touches the lightly-doped drain region, and a raised drain region that touches the heavily-doped drain region;   a channel region of the semiconductor region lying laterally between the source and the drain;   a gate dielectric touching and lying over the channel region; and   a gate touching and lying over the gate dielectric.   
     
     
         7 . The semiconductor structure of  claim 6  and further comprising a sidewall spacer being non-conductive, and touching and laterally surrounding the gate. 
     
     
         8 . The semiconductor structure of  claim 7  wherein the sidewall spacer touches the raised source region and the raised drain region. 
     
     
         9 . The semiconductor structure of  claim 7  wherein the sidewall spacer is spaced apart from the raised source region and the raised drain region. 
     
     
         10 . The semiconductor structure of  claim 6  wherein a top surface of the raised source region and a top surface of the raised drain region lie in a plane that passes through the gate, the plane lying above a bottom surface of the gate. 
     
     
         11 . A method of forming a semiconductor structure comprising:
 forming a gate structure that includes a gate dielectric that touches and lies above a semiconductor region, and a gate that touches and lies above the gate dielectric;   implanting the semiconductor region after the gate structure has been formed to form a lightly-doped source region and a lightly-doped drain region that touch the semiconductor region;   forming a first sidewall spacer that touches and laterally surrounds the gate structure;   implanting the semiconductor region, the lightly-doped source region, and the lightly-doped drain region after the first sidewall spacer has been formed to form a heavily-doped source region and a heavily-doped drain region, the heavily-doped source region touching the semiconductor region and the lightly-doped source region, the heavily-doped drain region touching the semiconductor region and the lightly-doped drain region;   forming a second sidewall spacer that touches and laterally surrounds the gate structure after the heavily-doped source region and the heavily-doped drain region have been formed; and   epitaxially growing a raised source region that touches the heavily-doped source region, and a raised drain region that touches the heavily-doped drain region after the second sidewall spacer has been formed.   
     
     
         12 . The method of  claim 11  and further comprising removing the first sidewall spacer after the heavily-doped source region and the heavily-doped drain region have been formed and before the second sidewall spacer is formed. 
     
     
         13 . The method of  claim 12  wherein the heavily-doped source region has a width, the raised source region has a width, and the width of the raised source region is greater than the width of the heavily-doped source region. 
     
     
         14 . The method of  claim 11  wherein forming the second sidewall spacer includes forming a third sidewall spacer to touch and laterally surround the first sidewall spacer, a combination of the first sidewall spacer and the third sidewall spacer forming the second sidewall spacer. 
     
     
         15 . The method of  claim 14  wherein the heavily-doped source region has a width, the raised source region has a width, and the width of the heavily-doped source region is substantially greater than the width of the raised source region. 
     
     
         16 . A method of forming a semiconductor structure comprising:
 forming a gate structure that includes a gate dielectric that touches and lies above a semiconductor region, and a gate that touches and lies above the gate dielectric;   implanting the semiconductor region after the gate structure has been formed to form a lightly-doped source region and a lightly-doped drain region that touch the semiconductor region;   forming a first sidewall spacer that touches and laterally surrounds the gate structure;   epitaxially growing a raised source region that touches the lightly-doped source region, and a raised drain region that touches the lightly-doped drain region after the first sidewall spacer has been formed;   forming a second sidewall spacer that touches and laterally surrounds the gate structure after the raised source region and the raised drain region have been formed; and   implanting the semiconductor region, the lightly-doped source region, and the lightly-doped drain region after the second sidewall spacer has been formed to form a heavily-doped source region and a heavily-doped drain region, the heavily-doped source region touching the semiconductor region, the lightly-doped source region, and the raised source region, the heavily-doped drain region touching the semiconductor region, the lightly-doped drain region, and the raised drain region.   
     
     
         17 . The method of  claim 16  and further comprising removing the first sidewall spacer after the raised source region and the raised drain region have been formed and before the second sidewall spacer is formed. 
     
     
         18 . The method of  claim 17  wherein the heavily-doped source region has a width, the raised source region has a width, and the width of the heavily-doped source region is substantially greater than the width of the raised source region. 
     
     
         19 . The method of  claim 16  wherein forming the second sidewall spacer includes forming a third sidewall spacer to touch and laterally surround the first sidewall spacer, a combination of the first sidewall spacer and the third sidewall spacer forming the second sidewall spacer. 
     
     
         20 . The method of  claim 19  wherein the heavily-doped source region has a width, the raised source region has a width, and the width of the raised source region is greater than the width of the heavily-doped source region.