Inventor · disambiguated record
Lee Evan Eisen
Also filed as: EISEN LEE · EISEN LEE E · EISEN LEE EVAN
55 granted patents·3 pending applications·573 citations·filing 1995–2023
98Inventor score
Top patents by PatentIndex Score
58 records- 0196US9672043B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 6, 2017·29 cites·8 claims
- 0296US7194645B2Method and apparatus for autonomic policy-based thermal management in a data processing systemIBM·Filed 2005·Granted Mar 20, 2007·63 cites·20 claims
- 0395US9690586B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 27, 2017·26 cites·4 claims
- 0495US9665372B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted May 30, 2017·25 cites·16 claims
- 0594US9690585B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted Jun 27, 2017·22 cites·9 claims
- 0692US9977678B2Reconfigurable parallel execution and load-store slice processorIBM·Filed 2015·Granted May 22, 2018·7 cites·10 claims
- 0790US9971602B2Reconfigurable processing method with modes controlling the partitioning of clusters and cache slicesIBM·Filed 2015·Granted May 15, 2018·6 cites·5 claims
- 0886US10083039B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Sep 25, 2018·3 cites·20 claims
- 0986US9141421B2Reducing power grid noise in a processor while minimizing performance lossIBM·Filed 2012·Granted Sep 22, 2015·8 cites·11 claims
- 1082US10983800B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Apr 20, 2021·2 cites·20 claims
- 1182US7392366B2Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetchesIBM·Filed 2005·Granted Jun 24, 2008·9 cites·26 claims
- 1281US10157064B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2017·Granted Dec 18, 2018·2 cites·15 claims
- 1379US7769984B2Dual-issuance of microprocessor instructions using dual dependency matricesIBM·Filed 2008·Granted Aug 3, 2010·9 cites·1 claims
- 1477US11074214B2Data processingADVANCED RISC MACH LTD·Filed 2019·Granted Jul 27, 2021·2 cites·13 claims
- 1577US7890738B2Method and logical apparatus for managing processing system resource use for speculative executionIBM·Filed 2005·Granted Feb 15, 2011·8 cites·21 claims
- 1676US10572259B2Hints in a data processing apparatusADVANCED RISC MACH LTD·Filed 2018·Granted Feb 25, 2020·2 cites·19 claims
- 1776US5805475ALoad-store unit and method of loading and storing single-precision floating-point registers in a double-precision architectureIBM·Filed 1997·Granted Sep 8, 1998·75 cites·21 claims
- 1875US8683180B2Intermediate register mapperBARRICK BRIAN D·Filed 2009·Granted Mar 25, 2014·8 cites·21 claims
- 1973US10635445B2Handling modifications to permitted program counter ranges in a data processing apparatusADVANCED RISC MACH LTD·Filed 2018·Granted Apr 28, 2020·2 cites·15 claims
- 2070US8464030B2Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bitsBUSABA FADI·Filed 2010·Granted Jun 11, 2013·3 cites·19 claims
- 2169US7549095B1Error detection enhancement in a microprocessor through the use of a second dependency matrixIBM·Filed 2008·Granted Jun 16, 2009·4 cites·1 claims
- 2269US6848044B2Circuits and methods for recovering link stack data upon branch instruction mis-speculationIBM·Filed 2001·Granted Jan 25, 2005·13 cites·19 claims
- 2366US10628157B2Early predicate look-upADVANCED RISC MACH LTD·Filed 2017·Granted Apr 21, 2020·1 cites·19 claims
- 2466US10102002B2Dynamic issue masks for processor hang preventionIBM·Filed 2014·Granted Oct 16, 2018·1 cites·7 claims
- 2565US9104399B2Dual issuing of complex instruction set instructionsBUSABA FADI·Filed 2009·Granted Aug 11, 2015·3 cites·19 claims
- 2664US11379228B2Microprocessor including an efficiency logic unitIBM·Filed 2019·Granted Jul 5, 2022·0 cites·6 claims
- 2763US7904697B2Load register instruction short circuiting methodIBM·Filed 2008·Granted Mar 8, 2011·2 cites·17 claims
- 2862US7254693B2Selectively prohibiting speculative execution of conditional branch type based on instruction bitIBM·Filed 2004·Granted Aug 7, 2007·8 cites·17 claims
- 2958US10514911B2Structure for microprocessor including arithmetic logic units and an efficiency logic unitIBM·Filed 2014·Granted Dec 24, 2019·0 cites·7 claims
- 3058US6442675B1Compressed string and multiple generation engineIBM·Filed 1999·Granted Aug 27, 2002·31 cites·10 claims
- 3155US9146772B2Reducing power grid noise in a processor while minimizing performance lossIBM·Filed 2013·Granted Sep 29, 2015·0 cites·9 claims
- 3255US5790445AMethod and system for performing a high speed floating point add operationIBM·Filed 1996·Granted Aug 4, 1998·29 cites·26 claims
- 3354US10503503B2Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unitIBM·Filed 2015·Granted Dec 10, 2019·0 cites·6 claims
- 3454US5619408AMethod and system for recoding noneffective instructions within a data processing systemIBM·Filed 1995·Granted Apr 8, 1997·24 cites·11 claims
- 3553US10108426B2Dynamic issue masks for processor hang preventionIBM·Filed 2015·Granted Oct 23, 2018·0 cites·7 claims
- 3653US2008133886A1Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetchesIBM·Filed 2007·Application pending·0 cites
- 3753US2008229068A1Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetchesIBM·Filed 2008·Application pending·0 cites
- 3852US2024319964A1Large number integer addition using vector accumulationADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 3951US6286094B1Method and system for optimizing the fetching of dispatch groups in a superscalar processorIBM·Filed 1999·Granted Sep 4, 2001·23 cites·5 claims
- 4050US6345356B1Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPsIBM·Filed 1999·Granted Feb 5, 2002·21 cites·18 claims
- 4149US9594561B2Instruction stream tracing of multi-threaded processorsIBM·Filed 2015·Granted Mar 14, 2017·0 cites·1 claims
- 4248US9996354B2Instruction stream tracing of multi-threaded processorsIBM·Filed 2015·Granted Jun 12, 2018·0 cites·19 claims
- 4347US11055096B2Checkpointing of architectural state for in order processing circuitryADVANCED RISC MACH LTD·Filed 2018·Granted Jul 6, 2021·0 cites·20 claims
- 4447US6321380B1Method and apparatus for modifying instruction operations in a processorIBM·Filed 1999·Granted Nov 20, 2001·18 cites·30 claims
- 4544US5897654AMethod and system for efficiently fetching from cache during a cache fill operationIBM·Filed 1997·Granted Apr 27, 1999·16 cites·12 claims
- 4643US10366741B2Bit processingADVANCED RISC MACH LTD·Filed 2017·Granted Jul 30, 2019·0 cites·20 claims
- 4743US9880847B2Register file mappingIBM·Filed 2015·Granted Jan 30, 2018·0 cites·17 claims
- 4843US5678016AProcessor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serializationIBM·Filed 1995·Granted Oct 14, 1997·16 cites·17 claims
- 4942US11030121B2Apparatus and method for comparing regions associated with first and second bounded pointersADVANCED RISC MACH LTD·Filed 2018·Granted Jun 8, 2021·0 cites·15 claims
- 5040US6385719B1Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessorIBM·Filed 1999·Granted May 7, 2002·12 cites·14 claims
Showing the top 50 of 58 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →