Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches

Abstract

A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.

1 - 19 . (canceled) 
   
   
       20 . A method of fetch gating an instruction cache, said method comprising the steps of:
 a) monitoring a plurality of event and use (EU) signals;   b) determining during each current clock preiod from said plurality of event and use (EU) signals whether to fetch from an instruction cache;   c) determining an execution thread designated for a next said fetch;   d) selecting contents of said instruction cache for said fetch; and   e) fetching said contents and passing said selected contents to the designated said execution thread.   
   
   
       21 . A method of fetch gating an instruction cache as in  claim 20 , wherein the step (b) of determining whether to fetch comprises the steps of:
 i) checking said a plurality of EU signals for a flow rate mismatch;   ii) checking said a plurality of EU signals for the occurrence of a Data/Instruction (D/I) cache miss;   iii) checking for a branch mis-prediction; and   iv) determining said designated execution thread for said selected contents.   
   
   
       22 . A method of fetch gating an instruction cache as in  claim 21 , wherein if a flow rate mismatch is not found in step (i), said method comprises proceeding to step (iii) and checking for a branch mis-prediction. 
   
   
       23 . A method of fetch gating an instruction cache as in  claim 21 , wherein if a D/I cache miss is found in said designated execution thread in step (ii), contents fetched and passed in step (v) are for another said execution thread. 
   
   
       24 . A method of fetch gating an instruction cache as in  claim 23 , wherein if a D/I cache miss is found for all said execution threads in step (ii), said method comprises returning to step (i) for a next said clock period. 
   
   
       25 . A method of fetch gating an instruction cache as in  claim 20 , wherein the step (b) of determining whether to fetch comprises checking said a plurality of EU signals for an indication that each execution thread has exceeded a threshold capacity. 
   
   
       26 . A method of fetch gating an instruction cache as in  claim 25 , wherein if all execution threads have not exceeded said threshold capacity, selecting one of said execution threads below said threshold capacity in step (c). 
   
   
       27 . A method of fetch gating an instruction cache as in  claim 26 , wherein before selecting said one in step (c) the said one is checked for a branch mis-prediction. 
   
   
       28 . A method of fetch gating an instruction cache as in  claim 27 , wherein if all execution thread have exceeded said threshold capacity and a mis-prediction is not found fetching in step (e) is skipped until a next said clock period.