Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches

Abstract

A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.

1 . A multithreaded processor comprising:
 an instruction cache with a plurality of cache locations;   a thread selection and priority circuit configured to monitor processor flags and selectively retrieve contents of each of said plurality of cache locations;   an instruction fetch unit pipeline configured to receive the selectively retrieved contents from said thread selection and priority circuit; and   a plurality of instruction buffer threads, wherein each of the selectively retrieved contents are passed to one of the instruction buffer threads through said instruction fetch unit pipeline, the thread selection and priority circuit being further configured to retrieve contents only for threads indicated by the processor flags as being capable of receiving the selectively retrieved contents.   
   
   
       2 . A multithreaded processor as in  claim 1 , wherein said processor flags include pipeline stall flags, flow mismatch flags, and utilization flags. 
   
   
       3 . A multithreaded processor as in  claim 2 , wherein said processor flags further include thread priority flags. 
   
   
       4 . A multithreaded processor as in  claim 1 , wherein said thread selection and priority circuit comprises an instruction cache fetch control circuit receiving said processor flags and determining whether contents are fetched from said instruction cache and further selecting instruction cache contents being fetched. 
   
   
       5 . A multithreaded processor as in  claim 4 , wherein said instruction cache fetch control circuit is a state machine. 
   
   
       6 . A multithreaded processor as in  claim 5 , wherein said state machine comprises:
 means for determining flow rate mismatch in said pipeline from said flags;   means for determining Data/Instruction (D/I) cache misses, responsive to a flow rate mismatch;   means for determining a branch mis-prediction responsive to said flags;   means for determining a next thread responsive to said means for flow rate mismatch determination and said means for D/I cache miss determination; and   means for indicating a next thread.   
   
   
       7 . A multithreaded processor as in  claim 5 , wherein said state machine comprises:
 means for determining whether each thread is at or above a high water mark;   means for determining a mis-prediction responsive to said flags;   means for determining a next thread responsive to said means for determining a mis-prediction; and   means for indicating a next thread.   
   
   
       8 . A multithreaded processor as in  claim 4 , wherein said instruction cache fetch control circuit provides a fetch gate signal and a thread identification to said cache responsive to said flags. 
   
   
       9 . A multithreaded processor as in  claim 8 , wherein said fetch gate signal is combined with a dispatch stall signal, a flow rate mismatch flag being provided from the combination. 
   
   
       10 . A multithreaded processor as in  claim 1 , wherein said multithreaded processor is a Simultaneous MultiThreaded (SMT) processor. 
   
   
       11 . An instruction fetch controller connectable between an instruction cache and a plurality of instruction buffers, said instruction fetch controller comprising:
 one or more inputs, each connected to an instruction cache port, each input receiving instructions from one or more threads stored in respective instruction cache banks;   one or more instruction outputs, each selectively providing one or more fetched instructions to a corresponding instruction buffer; and   one or more control inputs providing receiving event and use (EU) signals, said EU signals selecting in any clock cycle whether an instruction is fetched from the instruction cache.   
   
   
       12 . An instruction fetch controller as in  claim 11 , where the EU signals further controlling fetch selection priority and the instruction fetch controller selects which instructions are fetched in each clock cycle responsive to said EU signals whenever instructions are fetched. 
   
   
       13 . An instruction fetch controller as in  claim 11 , where the EU signals are selected from the group comprising: a signal indicating level of a queue, a stall event indicator, a thread priority indicator, an information flow rate indicator, a status flag, a pipeline stall condition indicator, a logical input indicator, a function input indicator, statistical indication signal, a historical state signal, and a state signal. 
   
   
       14 . An instruction fetch controller as in  claim 13 , wherein the stall event indicator is selected from the group comprising: a branch mis-prediction indicator, a cache miss indicator, an execution pipeline stall indicator, a dependence-related dispatch stall indicator, a resource-conflict stall indicator, and a pipeline flush-and-replay stall indicator. 
   
   
       15 . An instruction fetch controller as in  claim 13 , wherein the signal indicating level of the queue is a high watermark indicator for a buffer selected from the group comprising: an instruction fetch buffer, a load buffer, a store buffer, and an issue buffer. 
   
   
       16 . An instruction fetch controller as in  claim 11 , wherein one or more of the EU signals are dispatch stage thread priority signals. 
   
   
       17 . An instruction fetch controller as in  claim 16 , wherein the dispatch stage thread priority signals are asserted by software. 
   
   
       18 . An instruction fetch controller as in  claim 17 , wherein the dispatch stage thread priority signals are hardware generated signals. 
   
   
       19 . An instruction fetch controller as in  claim 16 , wherein the dispatch stage thread priority signals indicate an encoding order for considering threads in selecting cache contents and dispatching selected contents for execution in a given cycle. 
   
   
       20 . A Simultaneous MultiThreaded (SMT) processor comprising:
 an instruction cache with a plurality of cache locations;   an instruction fetch unit pipeline configured to receive selectively retrieved cache contents;   a plurality of instruction buffers, each selectively receiving data and instructions from said instruction fetch unit pipeline, wherein said instruction fetch unit pipeline is between said instruction cache and said plurality of instruction buffers, cache contents received by each of said plurality of instruction buffers passing through said instruction fetch unit pipeline to a respective instruction buffer;   an plurality of instruction buffer threads, each of said plurality of instruction buffer threads traversing one of said plurality of instruction buffers; and   a thread selection and priority circuit monitoring event and use (EU) flag signals for an indication of ones of said plurality of instruction buffers being capable of receiving retrieved cache contents, said thread selection and priority circuit selecting cache content locations being fetched and retrieving said cache contents from selected said cache content locations for a thread traversing an indicated one.   
   
   
       21 . A SMT processor as in  claim 20 , wherein said thread selection and priority circuit comprises an instruction cache fetch control circuit receiving said EU flags and determining whether contents are fetched from said instruction cache and further selecting instruction said cache content locations. 
   
   
       22 . A SMT processor as in  claim 21 , wherein said instruction cache fetch control circuit is a state machine comprising:
 means for determining flow rate mismatch in said pipeline from said EU flags;   means for determining Data/Instruction (D/I) cache misses, responsive to a flow rate mismatch;   means for determining a branch mis-prediction responsive to said EU flags;   means for determining a next thread responsive to said means for flow rate mismatch determination and said means for D/I cache miss determination; and   means for indicating a next thread.   
   
   
       23 . A SMT processor as in  claim 21 , wherein said instruction cache fetch control circuit is a state machine comprising:
 means for determining whether each thread is at or above a high water mark;   means for determining a mis-prediction responsive to said EU flags;   means for determining a next thread responsive to said means for determining a mis-prediction; and   means for indicating a next thread.   
   
   
       24 . A SMT processor as in  claim 21 , wherein said instruction cache fetch control circuit provides a fetch gate signal and a thread identification to said cache responsive to said EU flags. 
   
   
       25 . A SMT processor as in  claim 24 , wherein said fetch gate signal is combined with a dispatch stall signal, a flow rate mismatch flag being provided from the combination. 
   
   
       26 . A SMT processor as in  claim 21 , wherein said EU flags include pipeline stall flags, flow mismatch flags, utilization flags and thread priority flags.