Inventor · disambiguated record
Paul S. Zuchowski
Also filed as: ZUCHOWSKI PAUL S · ZUCHOWSKI PAUL STEVEN
49 granted patents·3 pending applications·974 citations·filing 1996–2014
98Inventor score
Top patents by PatentIndex Score
52 records- 0195US6883152B2Voltage island chip implementationIBM·Filed 2004·Granted Apr 19, 2005·92 cites·20 claims
- 0295US6820240B2Voltage island chip implementationIBM·Filed 2002·Granted Nov 16, 2004·90 cites·14 claims
- 0394US6779163B2Voltage island design planningIBM·Filed 2002·Granted Aug 17, 2004·89 cites·31 claims
- 0489US6523154B2Method for supply voltage drop analysis during placement phase of chip designIBM·Filed 2000·Granted Feb 18, 2003·63 cites·15 claims
- 0586US7459958B2Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsIBM·Filed 2006·Granted Dec 2, 2008·14 cites·5 claims
- 0685US7096436B2Macro design techniques to accommodate chip level wiring and circuit placement across the macroIBM·Filed 2004·Granted Aug 22, 2006·32 cites·9 claims
- 0783US8589843B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Nov 19, 2013·4 cites·13 claims
- 0882US6725439B1Method of automated design and checking for ESD robustnessIBM·Filed 2000·Granted Apr 20, 2004·44 cites·19 claims
- 0981US6651230B2Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit designIBM·Filed 2001·Granted Nov 18, 2003·31 cites·21 claims
- 1080US7644327B2System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGAIBM·Filed 2008·Granted Jan 5, 2010·8 cites·7 claims
- 1180US6185722B1Three dimensional track-based parasitic extractionIBM·Filed 1998·Granted Feb 6, 2001·102 cites·28 claims
- 1279US8490045B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Jul 16, 2013·3 cites·22 claims
- 1379US6832361B2System and method for analyzing power distribution using static timing analysisIBM·Filed 2001·Granted Dec 14, 2004·27 cites·34 claims
- 1478US7759960B2Integrated circuit testing methods using well bias modificationIBM·Filed 2008·Granted Jul 20, 2010·7 cites·24 claims
- 1578US7696811B2Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsIBM·Filed 2007·Granted Apr 13, 2010·9 cites·16 claims
- 1678US6993692B2Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memoriesIBM·Filed 2003·Granted Jan 31, 2006·25 cites·21 claims
- 1776US8122409B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2007·Granted Feb 21, 2012·5 cites·10 claims
- 1876US7400162B2Integrated circuit testing methods using well bias modificationIBM·Filed 2003·Granted Jul 15, 2008·17 cites·6 claims
- 1976US6543040B1Macro design techniques to accommodate chip level wiring and circuit placement across the macroIBM·Filed 2000·Granted Apr 1, 2003·18 cites·53 claims
- 2076US6505324B1Automated fuse blow software systemIBM·Filed 2000·Granted Jan 7, 2003·28 cites·27 claims
- 2176US6490708B2Method of integrated circuit design by selection of noise tolerant gatesIBM·Filed 2001·Granted Dec 3, 2002·24 cites·32 claims
- 2276US6026224ARedundant viasIBM·Filed 1996·Granted Feb 15, 2000·84 cites·16 claims
- 2374US7849426B2Mechanism for detection and compensation of NBTI induced threshold degradationIBM·Filed 2007·Granted Dec 7, 2010·6 cites·13 claims
- 2474US7564256B2Integrated circuit testing methods using well bias modificationINTERNAT BUSINESS MACHINES COM·Filed 2008·Granted Jul 21, 2009·6 cites·2 claims
- 2574US6948146B2Simplified tiling pattern methodIBM·Filed 2003·Granted Sep 20, 2005·20 cites·22 claims
- 2671US9104832B1Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip designIBM·Filed 2014·Granted Aug 11, 2015·3 cites·20 claims
- 2770US8504971B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Aug 6, 2013·2 cites·16 claims
- 2870US7793163B2Method and system for extending the useful life of another systemIBM·Filed 2008·Granted Sep 7, 2010·4 cites·20 claims
- 2970US6194233B1Integrated circuit and method of manufacture for avoiding damage by electrostatic chargeIBM·Filed 1998·Granted Feb 27, 2001·38 cites·9 claims
- 3069US6470476B2Substitution of non-minimum groundrule cells for non-critical minimum groundrule cells to increase yieldIBM·Filed 2001·Granted Oct 22, 2002·14 cites·24 claims
- 3168US7486098B2Integrated circuit testing method using well bias modificationIBM·Filed 2007·Granted Feb 3, 2009·4 cites·1 claims
- 3266US8020137B2Structure for an on-demand power supply current modification system for an integrated circuitIBM·Filed 2007·Granted Sep 13, 2011·3 cites·6 claims
- 3364US7095063B2Multiple supply gate array backfill structureIBM·Filed 2003·Granted Aug 22, 2006·12 cites·8 claims
- 3464US6883155B2Macro design techniques to accommodate chip level wiring and circuit placement across the macroIBM·Filed 2003·Granted Apr 19, 2005·7 cites·13 claims
- 3563US7793251B2Method for increasing the manufacturing yield of programmable logic devicesIBM·Filed 2006·Granted Sep 7, 2010·4 cites·10 claims
- 3662US7437620B2Method and system for extending the useful life of another systemIBM·Filed 2005·Granted Oct 14, 2008·2 cites·8 claims
- 3762US7131074B2Nested voltage island architectureIBM·Filed 2003·Granted Oct 31, 2006·10 cites·24 claims
- 3859US7961932B2Method and apparatus for manufacturing diamond shaped chipsIBM·Filed 2007·Granted Jun 14, 2011·1 cites·4 claims
- 3959US7671666B2Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsIBM·Filed 2008·Granted Mar 2, 2010·1 cites·10 claims
- 4059US7373567B2System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGAIBM·Filed 2004·Granted May 13, 2008·7 cites·19 claims
- 4158US7428675B2Testing using independently controllable voltage islandsIBM·Filed 2003·Granted Sep 23, 2008·5 cites·18 claims
- 4254US7545165B2System architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuitIBM·Filed 2007·Granted Jun 9, 2009·2 cites·18 claims
- 4353US2008246533A1Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsBARROWS COREY KENNETH·Filed 2008·Application pending·0 cites
- 4453US2008284459A1Testing Using Independently Controllable Voltage IslandsIBM·Filed 2008·Application pending·0 cites
- 4552US6731154B2Global voltage buffer for voltage islandsIBM·Filed 2002·Granted May 4, 2004·5 cites·7 claims
- 4650US9372520B2Reverse performance binningGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 21, 2016·0 cites·18 claims
- 4748US7949978B2Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuitIBM·Filed 2007·Granted May 24, 2011·0 cites·5 claims
- 4846US7289659B2Method and apparatus for manufacturing diamond shaped chipsIBM·Filed 2003·Granted Oct 30, 2007·2 cites·23 claims
- 4944US8122165B2On-demand power supply current modification system and method for an integrated circuitBARROWS COREY K·Filed 2007·Granted Feb 21, 2012·0 cites·13 claims
- 5044US2010333058A1Method for increasing the manufacturing yield of programmable logic devicesIBM·Filed 2010·Application pending·0 cites
Showing the top 50 of 52 patent records by PatentIndex Score.
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