Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

Abstract

A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

1 . A circuit, comprising:
 a first set of field effect transistors (FETs) having a designed first threshold voltage and a second set of FETs having a designed second threshold voltage, said first threshold voltage different from said second threshold voltage;   a first monitor circuit containing at least one FET of said first set of FETs and a second monitor circuit containing at least one FET of said second set of FETs;   an adjustable voltage regulator having an adjustable well bias voltage regulator, an output of said well bias voltage regulator connected to wells of said second set of FETs, a voltage level of said output of said well bias regulator based on a control signal;   a compare circuit configured to generate a compare signal based on a performance measurement of an output signal of said first monitor circuit and on a performance measurement of an output signal of said second monitor circuit; and   a control unit configured to generate said control signal to said well bias voltage regulator based on said compare signal.   
   
   
       2 . The circuit of  claim 1 , wherein said compare circuit includes a first edge counter connected between said first monitor circuit and a first comparator, a second edge counter connected between a reference clock and said first comparator and third edge counter connected between said second monitor circuit and said comparator; and further including:
 a memory device containing a ratio of said first performance specifications of said first monitor circuit to a second performance specification of said second monitor device, said memory device coupled to said comparator.   
   
   
       3 . The circuit of  claim 2 , wherein said control unit is configured to generate said control signal such that a ratio of a performance of FETs of said first set of FETs and a performance of FETs of said second set of FETs is equal to a performance ratio specification or is within an acceptable tolerance range of said performance ratio specification 
   
   
       4 . The circuit of  claim 1 , wherein
 said compare circuit includes a first edge counter connected between said first monitor circuit and a first comparator and a second edge counter connected between a reference clock and said first comparator; and further including:   an additional compare circuit including a third edge counter connected between said second monitor circuit and a second comparator and a fourth edge counter connected between said reference clock and said second comparator; and   a first memory device containing a first performance specification for said first monitor circuit coupled to said first comparator and a second memory device containing a second performance specification for said second monitor circuit coupled to said second comparator.   
   
   
       5 . The circuit of  claim 4 , further including:
 an additional adjustable well bias voltage regulator, an output of said additional well bias voltage regulator connected to wells of said first set of FETs, a voltage level of said output of said additional well bias regulator based on an additional control signal, a voltage level of said output of said additional well bias regulator based on an additional control signal;   said compare circuit configured to generate said additional compare signal based on said performance measurement of said output signal of said first monitor circuit and on said performance measurement of an output signal of said second monitor circuit; and   said control unit configured to generate said additional control signal to said additional well bias voltage regulator based on said additional compare signal.   
   
   
       6 . The circuit of  claim 5 , wherein said control unit is configured to generate said control signal and said additional control signal such that a performance of FETs of said first set of FETs is equal to a first performance specification or is within an acceptable tolerance range of said first performance specification and such that a performance of FETs of said second set of FETs is equal to a second performance specification or is within an acceptable tolerance range of said second performance specification. 
   
   
       7 . The circuit of  claim 1 , further including:
 means for adjusting expected values of said performance measurements of said first and second monitor circuits based on a temperature of and supply voltage to said first and second monitor circuits.   
   
   
       8 . A method, comprising;
 providing a first set of field effect transistors (FETs) having a designed first threshold voltage and a second set of FETs having a designed second threshold voltage, said first threshold voltage different from said second threshold voltage;   providing a first monitor circuit containing at least one FET of said first set of FETs and a second monitor circuit containing at least one FET of said second set of FETs;   providing an adjustable voltage regulator having an adjustable well bias voltage regulator, an output of said well bias voltage regulator connected to wells of said second set of FETs, a voltage level of said output of said well bias regulator based on a control signal;   providing a compare circuit configured to generate a compare signal based on a performance measurement of an output signal of said first monitor circuit and on a performance measurement of an output signal of said second monitor circuit; and   providing a control unit configured to generate said control signal to said well bias voltage regulator based on said compare signal.   
   
   
       9 . The method of  claim 8 , wherein said compare circuit includes a first edge counter connected between said first monitor circuit and a first comparator, a second edge counter connected between a reference clock and said first comparator and third edge counter connected between said second monitor circuit and said comparator; and further including:
 providing a memory device containing a ratio of said first performance specifications of said first monitor circuit to a second performance specification of said second monitor device, said memory device coupled to said comparator.   
   
   
       10 . The method of  claim 9 , wherein said control unit is configured to generate said control signal such that a ratio of a performance of FETs of said first set of FETs and a performance of FETs of said second set of FETs is equal to a performance ratio specification or is within an acceptable tolerance range of said performance ratio specification. 
   
   
       11 . The method of  claim 8 , wherein said compare circuit includes a first edge counter connected between said first monitor circuit and a first comparator and a second edge counter connected between a reference clock and said first comparator; and further including:
 providing an additional compare circuit including a third edge counter connected between said second monitor circuit and a second comparator and a fourth edge counter connected between said reference clock and said second comparator; and   providing a first memory device containing a first performance specification for said first monitor circuit coupled to said first comparator and a second memory device memory containing a second performance specification for said second monitor circuit coupled to said second comparator.   
   
   
       12 . The method of  claim 11 , further including:
 providing an additional adjustable well bias voltage regulator, an output of said additional well bias voltage regulator connected to wells of said first set of FETs, a voltage level of said output of said additional well bias regulator based on an additional control signal, a voltage level of said output of said additional well bias regulator based on an additional control signal;   wherein said compare circuit is configured to generate said additional compare signal based on said performance measurement of said output signal of said first monitor circuit and on said performance measurement of an output signal of said second monitor circuit; and   wherein said control unit is configured to generate said additional control signal to said additional well bias voltage regulator based on said additional compare signal.   
   
   
       13 . The method of  claim 12 , wherein said control unit is configured to generate said control signal and said additional control signal such that a performance of FETs of said first set of FETs is equal to a first performance specification or is within an acceptable tolerance range of said first performance specification and such that a performance of FETs of said second set of FETs is equal to a second performance specification or is within an acceptable tolerance range of said second performance specification. 
   
   
       14 . The method of  claim 8 , further including:
 providing means for adjusting expected values of said performance measurements of said first and second monitor circuits based on a temperature of and supply voltage to said first and second monitor circuits.   
   
   
       15 . A method, comprising:
 (a) measuring a performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of said first set of FETs having a designed first threshold voltage;   (b) measuring a performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of said second set of FETs having a designed second threshold voltage, said second threshold voltage different from said first threshold voltage; and   (c) applying a bias voltage to wells of said FETs of said second set of FETs based on comparing said performances of said first and second monitor circuits measured in steps (a) and (b) to specified performances of said first and second monitor circuits.   
   
   
       16 . The method of  claim 15 , further including:
 (d) applying an additional bias voltage to wells of FETs of said first set of FETs based on said comparing said performances of said first and second monitor circuits measured in steps (a) and (b) to specified performances of said first and second monitor circuits.   
   
   
       17 . The method of  claim 16 , step (d) further including:
 causing a switching speed of FETs of said first set of FETs to be equal to a first performance specification or within an acceptable tolerance range of said first performance specification and causing a switching speed of FETs of said second set of FETs to be equal to a second performance specification or within an acceptable tolerance range of said second performance specification by said applying said bias voltage and said additional bias voltage.   
   
   
       18 . The method of  claim 16 , step (d) further including, incrementally increasing, incrementally decreasing or not incrementing said bias voltage and said additional bias voltage and repeating steps (a) through (d) continuously while power is applied to an integrated circuit containing said first and second monitor circuits. 
   
   
       19 . The method of  claim 15 , step (d) further including:
 causing a ratio of a switching speed of FETs of said first set of FETs and a switching speed of FETs of said second set of FETs to be equal to a performance ratio specification or within an acceptable tolerance range of said performance ratio specification by said applying said bias voltage.   
   
   
       20 . The method of  claim 15 , step (d) further including, incrementally increasing, incrementally decreasing or not incrementing said bias voltage and repeating steps (a) through (d) continuously while power is applied to an integrated circuit containing said first and second monitor circuits.