Method for increasing the manufacturing yield of programmable logic devices

Abstract

A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

1 . A method for increasing the manufacturing yield of a field programmable gate array (FPGA) integrated circuit comprising:
 configuring the FPGA in a first section and a second section, each section having independent power and input/output (I/O) connections;   testing the FPGA in the first section and the second section to identify defects and characterize each section as at least one of a functional section and a non-functional section;   sorting the FPGA in accordance with the functional and non-functional test results; and   assigning a code to the FPGA corresponding to the functional and non-functional test results.   
     
     
         2 . The method according to  claim 1 , wherein said sorting step comprises:
 identifying each defective section as pre-existing logic which can not be used by a customer; and   providing FPGA software that targets only functional sections.   
     
     
         3 . The method according to  claim 1 , wherein the functional section having an acceptable number of defects is further tested for defects in power connections, critical global signals and control logic. 
     
     
         4 . The method according to  claim 1 , wherein each FPGA is identified with a unique programming code for downstream programming of only functional sections. 
     
     
         5 . The method according to  claim 1 , wherein the testing step further comprises verifying the integrity of the power supply bus and I/O connections. 
     
     
         6 . A method for increasing the manufacturing yield of a field programmable logic array (FPGA) comprising:
 dividing said FPGA into sections, each section having separate power busses and I/O busses;   testing each section of the FPGA to determine if one or more sections have an unacceptable level of defects; and   when one of the sections has an unacceptable level of defects, bonding external connections to said power bus and I/O bus of only one or more the sections that have an acceptable level of defects.   
     
     
         7 . The method according to  claim 6 , further comprising:
 forming programmable fusable links connecting configuration and any necessary control and I/O signals to each section; and   ablating a fusible link that is connected to a section having an unacceptable level of defects.   
     
     
         8 . The method according to  claim 7 , further comprising:
 configuring I/O connections to said section having an acceptable level of defects.   
     
     
         9 . The method according to  claim 7 , further comprising:
 forming programmable steering logic on the FPGA for steering configuration bits to functional regions of the FPGA.   
     
     
         10 . A method for increasing the manufacturing yield of a field programmable gate arrays (FPGA) comprising:
 forming an FPGA in a first section and a second section;   forming a first section configuration port and a second section configuration port on the FPGA for configuring the first section and second section, respectively;   testing each of the first section and second section to determine if one of the sections is defective;   configuring the first section with a configuration port when the second section is defective; and   configuring the second section with a configuration port when the first section is defective.   
     
     
         11 .- 13 . (canceled) 
     
     
         14 . A method for improving the usability of a field programmable logic array (FPGA) by constructing the FPGA in such a manner that connections to external circuitry for a given orientation are the same as when the FPGA is rotated 180° or smaller increments, wherein the increments are dependent on hardware implementation requirements. 
     
     
         15 .- 20 . (canceled)