Inventor · disambiguated record
Allen H. Gabor
Also filed as: GABOR ALLEN · GABOR ALLEN H
42 granted patents·4 pending applications·397 citations·filing 1992–2023
98Inventor score
Top patents by PatentIndex Score
46 records- 0198US9472506B2Registration mark formation during sidewall image transfer processIBM·Filed 2015·Granted Oct 18, 2016·26 cites·7 claims
- 0297US7147976B2Binary OPC for assist feature layout optimizationIBM·Filed 2005·Granted Dec 12, 2006·40 cites·6 claims
- 0396US7001693B2Binary OPC for assist feature layout optimizationIBM·Filed 2003·Granted Feb 21, 2006·70 cites·13 claims
- 0493US7799503B2Composite structures to prevent pattern collapseIBM·Filed 2007·Granted Sep 21, 2010·31 cites·24 claims
- 0591US8455162B2Alignment marks for multi-exposure lithographyGABOR ALLEN H·Filed 2011·Granted Jun 4, 2013·8 cites·15 claims
- 0687US9859224B2Registration mark formation during sidewall image transfer processIBM·Filed 2016·Granted Jan 2, 2018·3 cites·12 claims
- 0786US7083898B1Method for performing chemical shrink process over BARC (bottom anti-reflective coating)IBM·Filed 2005·Granted Aug 1, 2006·11 cites·20 claims
- 0885US6964032B2Pitch-based subresolution assist feature designIBM·Filed 2003·Granted Nov 8, 2005·26 cites·20 claims
- 0984US8673165B2Sidewall image transfer process with multiple critical dimensionsRAGHUNATHAN SUDHARSHANAN·Filed 2011·Granted Mar 18, 2014·11 cites·20 claims
- 1081US11239077B2Litho-etch-litho-etch with self-aligned blocksIBM·Filed 2019·Granted Feb 1, 2022·2 cites·20 claims
- 1181US8361683B2Multi-layer chip overlay target and measurementIBM·Filed 2010·Granted Jan 29, 2013·5 cites·15 claims
- 1280US7479355B1Mask design for enhancing line end resolutionIBM·Filed 2008·Granted Jan 20, 2009·5 cites·4 claims
- 1380US7288478B2Method for performing chemical shrink process over BARC (bottom anti-reflective coating)IBM·Filed 2005·Granted Oct 30, 2007·5 cites·7 claims
- 1479US7465615B1Polyconductor line end formation and related maskIBM·Filed 2007·Granted Dec 16, 2008·5 cites·1 claims
- 1577US7393703B2Method for reducing within chip device parameter variationsIBM·Filed 2006·Granted Jul 1, 2008·5 cites·22 claims
- 1676US8158334B2Methods for forming a composite pattern including printed resolution assist featuresGABOR ALLEN H·Filed 2008·Granted Apr 17, 2012·6 cites·20 claims
- 1774US7354779B2Topography compensated film application methodsIBM·Filed 2006·Granted Apr 8, 2008·4 cites·15 claims
- 1873US8293454B2Process of making a lithographic structure using antireflective materialsANGELOPOULOS MARIE·Filed 2008·Granted Oct 23, 2012·2 cites·25 claims
- 1971US6146793ARadiation sensitive terpolymer, photoresist compositions thereof and 193 nm bilayer systemsARCH SPEC CHEM INC·Filed 1999·Granted Nov 14, 2000·30 cites·18 claims
- 2070US7914975B2Multiple exposure lithography method incorporating intermediate layer patterningIBM·Filed 2007·Granted Mar 29, 2011·3 cites·16 claims
- 2169US8039203B2Integrated circuits and methods of design and manufacture thereofINFINEON TECHNOLOGIES AG·Filed 2008·Granted Oct 18, 2011·3 cites·26 claims
- 2267US7993815B2Line ends formingIBM·Filed 2007·Granted Aug 9, 2011·3 cites·13 claims
- 2367US7541613B2Methods for reducing within chip device parameter variationsIBM·Filed 2008·Granted Jun 2, 2009·2 cites·14 claims
- 2466US9046788B2Method for monitoring focus on an integrated waferGABOR ALLEN H·Filed 2008·Granted Jun 2, 2015·2 cites·21 claims
- 2565US5318877ABilayer resist and process for preparing sameCORNELL RES FOUNDATION INC·Filed 1993·Granted Jun 7, 1994·34 cites·16 claims
- 2665US5290397ABilayer resist and process for preparing sameCORNELL RES FOUNDATION INC·Filed 1992·Granted Mar 1, 1994·34 cites·9 claims
- 2764US7727825B2Polyconductor line end formation and related maskIBM·Filed 2008·Granted Jun 1, 2010·1 cites·15 claims
- 2864US7493186B2Method and algorithm for the control of critical dimensions in a thermal flow processIBM·Filed 2006·Granted Feb 17, 2009·2 cites·12 claims
- 2964US7485573B2Process of making a semiconductor device using multiple antireflective materialsIBM·Filed 2006·Granted Feb 3, 2009·1 cites·1 claims
- 3063US10242952B2Registration mark formation during sidewall image transfer processIBM·Filed 2018·Granted Mar 26, 2019·0 cites·14 claims
- 3162US2024319579A1Optimal scanner maps and field layoutsIBM·Filed 2023·Application pending·0 cites
- 3261US10043760B2Registration mark formation during sidewall image transfer processIBM·Filed 2017·Granted Aug 7, 2018·0 cites·9 claims
- 3360US8110496B2Method for performing chemical shrink process over BARC (bottom anti-reflective coating)BAILEY TODD CHRISTOPHER·Filed 2007·Granted Feb 7, 2012·1 cites·5 claims
- 3458US8609322B2Process of making a lithographic structure using antireflective materialsANGELOPOULOS MARIE·Filed 2012·Granted Dec 17, 2013·0 cites·17 claims
- 3557US8592110B2Alignment marks for multi-exposure lithographyIBM·Filed 2013·Granted Nov 26, 2013·0 cites·13 claims
- 3657US6296984B1Energy-sensitive resist material and a process for device fabrication using an energy-sensitive resist materialAGERE SYST GUARDIAN CORP·Filed 1999·Granted Oct 2, 2001·16 cites·28 claims
- 3756US12455505B2Method for forming continuous line-end to line-end spaces with spacer assisted lithography-etch-lithography etch processesIBM·Filed 2022·Granted Oct 28, 2025·0 cites·19 claims
- 3853US8847416B2Multi-layer chip overlay target and measurementIBM·Filed 2012·Granted Sep 30, 2014·0 cites·4 claims
- 3950US8491984B2Structure resulting from chemical shrink process over BARC (bottom anti-reflective coating)BAILEY TODD CHRISTOPHER·Filed 2011·Granted Jul 23, 2013·0 cites·14 claims
- 4050US2013181267A1Wafer fill patterns and usesIBM·Filed 2013·Application pending·0 cites
- 4148US10552569B2Method for calculating non-correctable EUV blank flatness for blank dispositioningGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 4, 2020·0 cites·20 claims
- 4247US2007015082A1Process of making a lithographic structure using antireflective materialsIBM·Filed 2005·Application pending·0 cites
- 4346US8507346B2Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layerBURKHARDT MARTIN·Filed 2010·Granted Aug 13, 2013·0 cites·4 claims
- 4442US9360858B2Alignment data based process control systemAUSSCHNITT CHRISTOPHER P·Filed 2011·Granted Jun 7, 2016·0 cites·25 claims
- 4542US2009065956A1Memory cellIBM·Filed 2007·Application pending·0 cites
- 4639US7968270B2Process of making a semiconductor device using multiple antireflective materialsIBM·Filed 2008·Granted Jun 28, 2011·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →